Issued Patents All Time
Showing 1–25 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369352 | Thin film transfer using substrate with etch stop layer and diffusion barrier layer | Eugene Chen, Chia-Shiung Tsai, Chen-Hao Chiang | 2025-07-22 |
| 12230585 | Photolithography alignment process for bonded wafers | Yeong-Jyh Lin, Ching-I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu +2 more | 2025-02-18 |
| 12211737 | Cleaning chamber for metal oxide removal | Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo-Liang Lu +1 more | 2025-01-28 |
| 12113071 | Multi-function substrate | Eugene Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Chih-Ping Chao +1 more | 2024-10-08 |
| 12040221 | Fabrication method of metal-free SOI wafer | Yu-Hung Cheng, Pu Chen, Cheng-Ta Wu, Po-Jung Chiang, Victor Lu +4 more | 2024-07-16 |
| 11916022 | Photolithography alignment process for bonded wafers | Yeong-Jyh Lin, Ching-I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu +2 more | 2024-02-27 |
| 11804531 | Thin film transfer using substrate with etch stop layer and diffusion barrier layer | Eugene Chen, Chia-Shiung Tsai, Chen-Hao Chiang | 2023-10-31 |
| 11735624 | Multi-lateral recessed MIM structure | Alexander Kalnitsky, Ming Chyi Liu, Sheng-Chan Li, Sheng-Chau Chen | 2023-08-22 |
| 11721752 | Semiconductor device having doped seed layer and method of manufacturing the same | Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai | 2023-08-08 |
| 11682578 | Multilayer isolation structure for high voltage silicon-on-insulator device | Yu-Hung Cheng, Yu-Chun Chang, Ching-I Li | 2023-06-20 |
| 11532642 | Multi-function substrate | Eugene Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Chih-Ping Chao +1 more | 2022-12-20 |
| 11404465 | Epitaxial semiconductor liner for enhancing uniformity of a charged layer in a deep trench and methods of forming the same | Yu-Hung Cheng, Yeur-Luen Tu | 2022-08-02 |
| 11374000 | Trench capacitor with lateral protrusion structure | Ming Chyi Liu, Shih-Chang Liu | 2022-06-28 |
| 11362038 | Photolithography alignment process for bonded wafers | Yeong-Jyh Lin, Ching-I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu +2 more | 2022-06-14 |
| 11329148 | Semiconductor device having doped seed layer and method of manufacturing the same | Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai | 2022-05-10 |
| 11232974 | Fabrication method of metal-free SOI wafer | Yu-Hung Cheng, Pu Chen, Cheng-Ta Wu, Po-Jung Chiang, Victor Lu +4 more | 2022-01-25 |
| 11167982 | Semiconductor arrangement and formation thereof | Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai | 2021-11-09 |
| 11145806 | Magnetic tunnel junction with reduced damage | Carlos H. Diaz, Harry-Hak-Lay Chuang | 2021-10-12 |
| 10991758 | Semiconductor structure | Harry-Hak-Lay Chuang, Kuei-Hung Shen, Hsun-Chung Kuang, Cheng-Yuan Tsai | 2021-04-27 |
| 10889097 | Wafer debonding system and method | Chang-Chen Tsao, Kuo-Liang Lu, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu +1 more | 2021-01-12 |
| 10868024 | Method of forming embedded nonvolatile memory | Chang-Ming Wu, Wei-Cheng Wu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai +1 more | 2020-12-15 |
| 10811504 | Semiconductor structure for flash memory cells and method of making same | Ming Chyi Liu, Chang-Ming Wu, Shih-Chang Liu, Wei-Cheng Wu, Harry-Hak-Lay Chuang +1 more | 2020-10-20 |
| 10683204 | Semiconductor arrangement and formation thereof | Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai | 2020-06-16 |
| 10672975 | Magnetic tunnel junction with reduced damage | Carlos H. Diaz, Harry-Hak-Lay Chuang | 2020-06-02 |
| 10569520 | Wafer debonding system and method | Chang-Chen Tsao, Kuo-Liang Lu, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu +1 more | 2020-02-25 |