Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8102033 | Reduced soft error rate through metal fill and placement | Alicia Wang | 2012-01-24 |
| 7888959 | Apparatus and method for hardening latches in SOI CMOS devices | Ethan H. Cannon, AJ KleinOsowski, Tak H. Ning, Philip J. Oldiges, Leon Sigal +2 more | 2011-02-15 |
| 7683434 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | Paul D. Agnello, Rajeev Malik | 2010-03-23 |
| 7645650 | Double gated transistor and method of fabrication | Andres Bryant, Meikei Ieong, Edward J. Nowak, David M. Fried, Jed H. Rankin | 2010-01-12 |
| 7627836 | OPC trimming for performance | James A. Culp, Lars Liebmann, Rajeev Malik, Shreesh Narasimha, Stephen L. Runyon +1 more | 2009-12-01 |
| 7491598 | CMOS circuits including a passive element having a low end resistance | Christopher D. Sheraw, Alyssa C. Bonnoit, Werner Rausch | 2009-02-17 |
| 7459384 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | Paul D. Agnello, Rajeev Malik | 2008-12-02 |
| 7361959 | CMOS circuits including a passive element having a low end resistance | Christopher D. Sheraw, Alyssa C. Bonnoit, Werner Rausch | 2008-04-22 |
| 7304352 | Alignment insensitive D-cache cell | Kevin A. Batson, Michael Ju Hyeok Lee | 2007-12-04 |
| 7288445 | Double gated transistor and method of fabrication | Andres Bryant, Meikei Ieong, Edward J. Nowak, David M. Fried, Jed H. Rankin | 2007-10-30 |
| 7087477 | FinFET SRAM cell using low mobility plane for cell stability and method for forming | David M. Fried, Randy W. Mann, Edward J. Nowak | 2006-08-08 |
| 6967351 | Finfet SRAM cell using low mobility plane for cell stability and method for forming | David M. Fried, Randy W. Mann, Edward J. Nowak | 2005-11-22 |
| 6960806 | Double gated vertical transistor with different first and second gate materials | Andres Bryant, Meikei Ieong, Edward J. Nowak, David M. Fried, Jed H. Rankin | 2005-11-01 |
| 6913960 | Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication | Andres Bryant, Edward J. Nowak | 2005-07-05 |
| 6774437 | Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication | Andres Bryant, Edward J. Nowak | 2004-08-10 |
| 6657261 | Ground-plane device with back oxide topography | Fariborz Assaderaghi, Tze-Chiang Chen, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi | 2003-12-02 |
| 6645795 | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator | Dominic J. Schepis, Ghavam G. Shahidi | 2003-11-11 |
| 6541317 | Polysilicon doped transistor | Dominic J. Schepis, Ghavam G. Shahidi | 2003-04-01 |
| 6537418 | Spatially uniform gas supply and pump configuration for large wafer diameters | Bertrand Flietner, Klaus Roithner | 2003-03-25 |
| 6534351 | Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices | Andre I. Nasr | 2003-03-18 |
| 6521949 | SOI transistor with polysilicon seed | Fariborz Assaderaghi, Tze-Chiang Chen, Edward J. Nowak, Ghavam G. Shahidi | 2003-02-18 |
| 6463184 | Method and apparatus for overlay measurement | Chris Gould, V. C. Jai Prakash, Robert Willem Van Den Berg | 2002-10-08 |
| 6432754 | Double SOI device with recess etch and epitaxy | Fariborz Assaderaghi, Tze-Chiang Chen, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi | 2002-08-13 |
| 6432829 | Process for making planarized silicon fin device | Edward J. Nowak, Hon-Sum Philip Wong | 2002-08-13 |
| 6291353 | Lateral patterning | Hon-Sum Philip Wong | 2001-09-18 |