Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10896707 | Selective clock adjustment during read and/or write memory operations | Rahul Mathur, Cyrille Dray, Yann Sarrazin, Julien Vincent Poitrat, Yannis Jallamion-Grive +4 more | 2021-01-19 |
| 10878893 | Control architecture for column decoder circuitry | Vianney Choserot, Sriram Thyagarajan, Yew Keong Chong, Munish Kumar | 2020-12-29 |
| 10847211 | Latch circuitry for memory applications | Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong | 2020-11-24 |
| 10847215 | Bitcell shifting technique | Yew Keong Chong | 2020-11-24 |
| 10839934 | Redundancy circuitry for memory application | Rahul Mathur, Gaurang Prabhakar Narvekar, Sanjay Mangal, Yew Keong Chong, Bikas Maiti +1 more | 2020-11-17 |
| 10817420 | Apparatus and method to access a memory location | Yew Keong Chong, Sriram Thyagarajan | 2020-10-27 |
| 10796053 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Brian Tracy Cline, Xiaoqing Xu +6 more | 2020-10-06 |
| 10756753 | Data compressor logic circuit | Shardendu Shekhar, Yew Keong Chong | 2020-08-25 |
| 10741227 | Clock generating circuitry | Kumaraswamy Ramanathan, Peixuan Tan | 2020-08-11 |
| 10672459 | Transition coupling circuitry for memory applications | Yicong Li, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park +2 more | 2020-06-02 |
| 10574236 | Level shifter with bypass control | Cagla Cakir | 2020-02-25 |
| 10535386 | Level shifter with bypass | Yew Keong Chong, Rahul Mathur, Abhishek Baradia, Hsin-Yu Chen | 2020-01-14 |
| 10425076 | Power-on-reset circuit | Lalit Gupta, Vivek Nautiyal, Jitendra Dasani, Bo Zheng, Akshay Kumar +1 more | 2019-09-24 |
| 10177760 | Circuit with impedance elements connected to sources and drains of pMOSFET headers | Yew Keong Chong, Yicong Li, Hsin-Yu Chen, Sriram Thyagarajan | 2019-01-08 |
| 10083269 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Brian Lee, Brian Tracy Cline +12 more | 2018-09-25 |
| 10033376 | Power-on-reset circuit | Lalit Gupta, Vivek Nautiyal, Jitendra Dasani, Bo Zheng, Akshay Kumar +1 more | 2018-07-24 |
| 10020031 | Location-based optimization for memory systems | Yew Keong Chong, Sriram Thyagarajan, Gus Yeung, James Dennis Dodrill | 2018-07-10 |
| 9891976 | Error detection circuitry for use with memory | Mudit Bhargava, Paul Gilbert Meyer, Vikas Chandra | 2018-02-13 |
| 9741410 | Memory circuitry using write assist voltage boost | Yew Keong Chong, Gus Yeung, Bo Zheng, George McNeil Lattimore | 2017-08-22 |
| 9721624 | Memory with multiple write ports | Gus Yeung, Fakhruddin Ali Bohra, Mudit Bhargava, Yew Keong Chong | 2017-08-01 |
| 9627022 | Double pumped memory techniques | Hsin-Yu Chen, Sabarish Ittamveetil, Yew Keong Chong, Indranil Basu, Yew Keong Vikash | 2017-04-18 |
| 9600179 | Access suppression in a memory device | Yew Keong Chong, Michael Filippo, Gus Yeung, Sriram Thyagarajan | 2017-03-21 |
| 9542986 | Low power input gating | Gus Yeung, Yew Keong Chong | 2017-01-10 |
| 9379710 | Level conversion circuit and method | Yew Keong Chong | 2016-06-28 |
| 9281027 | Test techniques in memory devices | Yew Keong Chong, Sriram Thyagarajan, Mudit Bhargava | 2016-03-08 |