Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11664086 | Column redundancy techniques | Yew Keong Chong, Andy Wangkun Chen, Bikas Maiti | 2023-05-30 |
| 11232833 | Dummy bitline circuitry | Abhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Satinderjit Singh, Vasimraja Bhavikatti | 2022-01-25 |
| 11043262 | Write assist circuitry | Arjunesh Namboothiri Madhavan, Akash Bangalore Srinivasa, Sujit Kumar Rout, Vikash, Gaurav Rattan Singla +3 more | 2021-06-22 |
| 10878892 | Integrated circuit using discharging circuitries for bit lines | Lalit Gupta, Jitendra Dasani, Shri Sagar Dwivedi, Fakhruddin Ali Bohra | 2020-12-29 |
| 10839861 | Routing structures for memory applications | Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon +2 more | 2020-11-17 |
| 10755774 | Coupling compensation circuitry | Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi | 2020-08-25 |
| 10748583 | Dummy bitline circuitry | Lalit Gupta, Jitendra Dasani, Fakhruddin Ali Bohra, Shri Sagar Dwivedi | 2020-08-18 |
| 10622038 | High-speed memory architecture | Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Gaurav Rattan Singla | 2020-04-14 |
| 10600477 | Coupling compensation circuitry | Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi | 2020-03-24 |
| 10425076 | Power-on-reset circuit | Lalit Gupta, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar +1 more | 2019-09-24 |
| 10269416 | Dummy wordline tracking circuitry | Lalit Gupta, Jitendra Dasani, Fakhruddin Ali Bohra | 2019-04-23 |
| 10217496 | Bitline write assist circuitry | Jitendra Dasani, Satinderjit Singh, Shri Sagar Dwivedi, Bo Zheng, Fakhruddin Ali Bohra | 2019-02-26 |
| 10147482 | Skewed corner tracking for memory write operations | Jitendra Dasani, Shri Sagar Dwivedi, Fakhruddin Ali Bohra | 2018-12-04 |
| 10074410 | Integrated circuit using shaping and timing circuitries | Jitendra Dasani, Fakhruddin Ali Bohra, Satinderjit Singh, Shri Sagar Dwivedi | 2018-09-11 |
| 10033376 | Power-on-reset circuit | Lalit Gupta, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar +1 more | 2018-07-24 |
| 9911510 | Redundancy schemes for memory cell repair | Jungtae Kwon, Young Suk Kim, Pranay Prabhat, Fakhruddin Ali Bohra, Shri Sagar Dwivedi +2 more | 2018-03-06 |
| 9824749 | Read assist circuitry | Fakhruddin Ali Bohra, Satinderjit Singh, Shri Sagar Dwivedi, Abhishek B. Akkur | 2017-11-21 |
| 9711243 | Redundancy schemes for memory | Fakhruddin Ali Bohra, Satinderjit Singh, Jitendra Dasani, Shri Sagar Dwivedi | 2017-07-18 |
| 8223574 | Techniques for block refreshing a semiconductor memory device | Serguei Okhonin | 2012-07-17 |
| 7433239 | Memory with reduced bitline leakage current and method for the same | Ashish Kumar | 2008-10-07 |
| 7420859 | Memory device and method of controlling access to such a memory device | — | 2008-09-02 |
| 7379347 | Memory device and method for performing write operations in such a memory device | — | 2008-05-27 |
| 7372764 | Logic device with reduced leakage current | Ashish Kumar | 2008-05-13 |
| 7116137 | Method and system for reducing power consumption in digital circuitry using charge redistribution circuits | Ashish Kumar | 2006-10-03 |
| 7035132 | Memory architecture for increased speed and reduced power consumption | Ashish Kumar | 2006-04-25 |