Issued Patents All Time
Showing 25 most recent of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12421604 | Ultra-shallow dopant and ohmic contact regions by solid state diffusion | — | 2025-09-23 |
| 12406887 | Selective film formation using a self-assembled monolayer | Dina H. Triyoso, Lior Huli, Corey Lemley, Gerrit J. Leusink | 2025-09-02 |
| 12372871 | EUV active films for EUV lithography | — | 2025-07-29 |
| 12362304 | Bonding layer and process of making | — | 2025-07-15 |
| 12272601 | Epitaxial high-K etch stop layer for backside reveal integration | — | 2025-04-08 |
| 12261209 | Replacement channel 2D material integration | H. Jim Fulford, Mark I. Gardner | 2025-03-25 |
| 12237216 | Method for filling recessed features in semiconductor devices with a low-resistivity metal | Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han +5 more | 2025-02-25 |
| 12211907 | Semiconductor manufacturing platform with in-situ electrical bias and methods thereof | Dina H. Triyoso, David Hurley, Ian Colgan | 2025-01-28 |
| 12191297 | Facilitating alignment of stacked chiplets | — | 2025-01-07 |
| 12148625 | Methods to prevent surface charge induced cd-dependent etching of material formed within features on a patterned substrate | Shan Hu, Henan Zhang, Sangita Kumari, Peter Delia | 2024-11-19 |
| 11978735 | Transistor stack of vertical channel ferroelectric FETs and methods of forming the transistor stack | Mark I. Gardner, H. Jim Fulford | 2024-05-07 |
| 11967640 | Crystalline dielectric systems for interconnect circuit manufacturing | — | 2024-04-23 |
| 11942536 | Semiconductor device having channel structure with 2D material | H. Jim Fulford, Mark I. Gardner | 2024-03-26 |
| 11894240 | Semiconductor processing systems with in-situ electrical bias | David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes +6 more | 2024-02-06 |
| 11769677 | Substrate processing tool with integrated metrology and method of using | Kandabara Tapily | 2023-09-26 |
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Anton J. deVilliers | 2023-09-19 |
| 11621190 | Method for filling recessed features in semiconductor devices with a low-resistivity metal | Kai-Hung Yu, David L. O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Kandabara Tapily +3 more | 2023-04-04 |
| 11594451 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Kandabara Tapily, Kai-Hung Yu | 2023-02-28 |
| 11462414 | Atomic layer etching of metal oxides | — | 2022-10-04 |
| 11456212 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Kandabara Tapily, Kai-Hung Yu | 2022-09-27 |
| 11424236 | Facilitating alignment of stacked chiplets | — | 2022-08-23 |
| 11398379 | Platform and method of operating for integrated end-to-end self-aligned multi-patterning process | Richard A. Farrell, Kandabara Tapily, Angelique Raley, Sophie Thibaut | 2022-07-26 |
| 11302588 | Platform and method of operating for integrated end-to-end area-selective deposition process | Kandabara Tapily, Jason Mehigan | 2022-04-12 |
| 11264254 | Substrate processing tool with integrated metrology and method of using | Kandabara Tapily | 2022-03-01 |
| 11152268 | Platform and method of operating for integrated end-to-end area-selective deposition process | Kandabara Tapily, Jason Mehigan | 2021-10-19 |