Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7030017 | Method for the planarization of a semiconductor structure | Mark Hollatz, Klaus-Dieter Morhard, Alexander Truby | 2006-04-18 |
| 7012003 | Memory for producing a memory component | — | 2006-03-14 |
| 6803612 | Integrated circuit having electrical connecting elements | Matthias Lehr, Jens Mockel | 2004-10-12 |
| 6765248 | Field effect transistor and fabrication method | Thomas Schuster | 2004-07-20 |
| 6492282 | Integrated circuits and manufacturing methods | Peter Weigand, Matthias Ilg | 2002-12-10 |
| 6465282 | Method of forming a self-aligned antifuse link | Axel Brintzinger, Stefan Weber | 2002-10-15 |
| 6426254 | Method for expanding trenches by an anisotropic wet etch | Stephen Kudelka, Alexander Michaelis | 2002-07-30 |
| 6404000 | Pedestal collar structure for higher charge retention time in trench-type DRAM cells | Rama Divakaruni, Rajarao Jammy, Byeong Y. Kim, Jack A. Mandelman, Akira Sudo | 2002-06-11 |
| 6271142 | Process for manufacture of trench DRAM capacitor buried plates | Ulrike Gruening, Carl Radens | 2001-08-07 |
| 6261950 | Self-aligned metal caps for interlevel metal connections | Jeffrey P. Gambino | 2001-07-17 |
| 6261937 | Method for forming a semiconductor fuse | Stefan Weber, Axel Brintzinger | 2001-07-17 |
| 6245629 | Semiconductor structures and manufacturing methods | — | 2001-06-12 |
| 6235574 | High performance DRAM and method of manufacture | Johann Alsmeier | 2001-05-22 |
| 6184091 | Formation of controlled trench top isolation layers for vertical transistors | Ulrike Gruening, Jochen Beintner, Gill Yong Lee, Oswald Spindler, Zvonimir Gabric | 2001-02-06 |
| 6177698 | Formation of controlled trench top isolation layers for vertical transistors | Ulrike Gruening, Jochen Beintner, Gill Yong Lee, Oswald Spindler, Zvonimir Gabric | 2001-01-23 |
| 6103456 | Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication | Gill Yong Lee | 2000-08-15 |
| 6066569 | Dual damascene process for metal layers and organic intermetal layers | — | 2000-05-23 |
| 6046503 | Metalization system having an enhanced thermal conductivity | Peter Weigand | 2000-04-04 |
| 6037648 | Semiconductor structure including a conductive fuse and process for fabrication thereof | Kenneth C. Arndt, Jeffrey P. Gambino, Jack A. Mandelman, Chandrasekhar Narayan, Rainer Florian Schnabel +1 more | 2000-03-14 |
| 6033977 | Dual damascene structure | Martin Gutsche | 2000-03-07 |
| 6015988 | Microstructure and methods for fabricating such structure | Peter Weigand | 2000-01-18 |
| 6001740 | Planarization of a non-conformal device layer in semiconductor fabrication | Kathryn H. Varian, Matthew Sendelbach | 1999-12-14 |
| 5977635 | Multi-level conductive structure including low capacitance material | Peter Weigand | 1999-11-02 |
| 5963837 | Method of planarizing the semiconductor structure | Matthias Ilg, Peter Weigand | 1999-10-05 |
| 5926716 | Method for forming a structure | Peter Weigand | 1999-07-20 |