Issued Patents All Time
Showing 351–375 of 404 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6409904 | Method and apparatus for depositing and controlling the texture of a thin film | Homayoun Talieh | 2002-06-25 |
| 6406608 | Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal | Wilma Jean Horkans, Panayotis Andricacos | 2002-06-18 |
| 6399496 | Copper interconnection structure incorporating a metal seed layer | Daniel C. Edelstein, James M. E. Harper, Chao-Kun Hu, Andrew H. Simon | 2002-06-04 |
| 6380628 | Microstructure liner having improved adhesion | John A. Miller, Andrew H. Simon, Jill Slattery, Yun-Yu Wang | 2002-04-30 |
| 6372081 | Process to prevent copper contamination of semiconductor fabs | L. Paivikki Buchwalter | 2002-04-16 |
| 6355153 | Chip interconnect and packaging deposition methods and structures | Homayoun Talieh, Bulent M. Basol | 2002-03-12 |
| 6354916 | Modified plating solution for plating and planarization and process utilizing same | Bulent M. Basol, Homayoun Talieh | 2002-03-12 |
| 6352623 | Vertically configured chamber used for multiple processes | Konstantin Volodarsky, Boguslaw Nagorski, Rimma Volodarsky, Douglas W. Young, Homayoun Talieh | 2002-03-05 |
| 6344129 | Method for plating copper conductors and devices formed | Kenneth P. Rodbell, Panayotis Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Peter S. Locke | 2002-02-05 |
| 6339258 | Low resistivity tantalum | Edward C. Cooney, III | 2002-01-15 |
| 6337218 | Method to test devices on high performance ULSI wafers | Stephen A. Cohen, Arnold Halperin | 2002-01-08 |
| 6337151 | Graded composition diffusion barriers for chip wiring applications | Daniel C. Edelstein, Andrew H. Simon | 2002-01-08 |
| 6333120 | Method for controlling the texture and microstructure of plated copper and plated structure | Patrick W. DeHaven, Peter S. Locke, Kenneth P. Rodbell | 2001-12-25 |
| 6333560 | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies | — | 2001-12-25 |
| 6331237 | Method of improving contact reliability for electroplating | Panayotis Andricacos, W. Jean Horkans, Keith Kwietniak, Peter S. Locke | 2001-12-18 |
| 6328872 | Method and apparatus for plating and polishing a semiconductor substrate | Homayoun Talieh | 2001-12-11 |
| 6297140 | Method to plate C4 to copper stud | Daniel C. Edelstein | 2001-10-02 |
| 6291885 | Thin metal barrier for electrical interconnections | Cyril Cabral, Jr., Patrick W. DeHaven, Daniel C. Edelstein, David P. Klaus, James Manley Pollard, III +1 more | 2001-09-18 |
| 6274935 | Copper wire-bonding pad | — | 2001-08-14 |
| 6270646 | Electroplating apparatus and method using a compressible contact | Erick G. Walton, Dean S. Chung, Lara Sandra Collins, William E. Corbin, Jr., Hariklia Deligianni +4 more | 2001-08-07 |
| 6261426 | Method and apparatus for enhancing the uniformity of electrodeposition or electroetching | Hariklia Deligianni, John O. Dukovic | 2001-07-17 |
| 6258707 | Triple damascence tungsten-copper interconnect structure | — | 2001-07-10 |
| 6258717 | Method to produce high quality metal fill in deep submicron vias and lines | Peter S. Locke | 2001-07-10 |
| 6251528 | Method to plate C4 to copper stud | Daniel C. Edelstein | 2001-06-26 |
| 6251251 | Anode design for semiconductor deposition | Panayotis Andricacos, John O. Dukovic, Robert P. Westerfield, Jr. | 2001-06-26 |