Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11448692 | Method and device for wafer-level testing | Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu | 2022-09-20 |
| 11423957 | Sense amplifier, memory and method for controlling a sense amplifier | Chunyu Peng, Junlin Ge, Zhan Ying, Xin Li, Kanyu Cao +4 more | 2022-08-23 |
| 11387182 | Module structure and method for manufacturing the module structure | Chengjie Zuo | 2022-07-12 |
| 11315610 | Sense amplifier, memory and method for controlling sense amplifier | Chunyu Peng, Zijian Wang, Wenjuan Lu, Xiulong Wu, Xin Li +4 more | 2022-04-26 |
| 11221362 | Integrated circuit and test method for integrated circuit | Chengjie Zuo | 2022-01-11 |
| 11190160 | Frequency multiplexer | Xiaodong Wang, Chengjie Zuo | 2021-11-30 |
| 11081392 | Dicing method for stacked semiconductor devices | Tsung-Hsing Lu, Li-Huan Chu, Pei-Haw Tsao | 2021-08-03 |
| 11073551 | Method and system for wafer-level testing | Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu | 2021-07-27 |
| D924186 | Board card | Xiaobing Feng, Kun He | 2021-07-06 |
| 10923461 | Light-emitting module and tandem light-emitting device | Chien-Chung Huang, Hsin-Nu Li | 2021-02-16 |
| 10811363 | Marks for locating patterns in semiconductor fabrication | Dou Zhang, Jin Yu Qiu, Zhi Yang Song, Zhi Hu Gao, Yaobin Feng | 2020-10-20 |
| 9984922 | Interconnects having sealing structures to enable selective metal capping layers | Kevin J. Fischer, Ying Zhou, Peter K. Moon | 2018-05-29 |
| 9461010 | Debond interconnect structures | Qing Ma, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan +2 more | 2016-10-04 |
| 9437545 | Interconnects having sealing structures to enable selective metal capping layers | Kevin J. Fischer, Ying Zhou, Peter K. Moon | 2016-09-06 |
| 9269686 | Debond interconnect structures | Qing Ma, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan +2 more | 2016-02-23 |
| 8928125 | Interconnects having sealing structures to enable selective metal capping layers | Kevin J. Fischer, Ying Zhou, Peter K. Moon | 2015-01-06 |
| 8703547 | Thyristor comprising a special doped region characterized by an LDD region and a halo implant | Yi Shan | 2014-04-22 |
| 8704336 | Selective removal of on-die redistribution interconnects from scribe-lines | Kevin J. Lee, Subhash M. Joshi | 2014-04-22 |
| 8637778 | Debond interconnect structures | Qing Ma, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan +2 more | 2014-01-28 |
| 8368171 | Methods of forming electromigration and thermal gradient based fuse structures | Jose Maiz, Mark Bohr | 2013-02-05 |
| 8331186 | Fuse programming schemes for robust yield | Zhanping Chen, Jeffrey Hicks, Gregory F. Taylor | 2012-12-11 |
| 8242831 | Tamper resistant fuse design | Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson | 2012-08-14 |
| 8058710 | Interconnects having sealing structures to enable selective metal capping layers | Kevin J. Fischer, Ying Zhou, Peter K. Moon | 2011-11-15 |
| 7889587 | Fuse programming schemes for robust yield | Zhanping Chen, Jeffrey Hicks, Gregory F. Taylor | 2011-02-15 |
| 7889013 | Microelectronic die having CMOS ring oscillator thereon and method of using same | Gerald S. Leatherman, Jose Maiz | 2011-02-15 |