Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12313675 | Method and device for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2025-05-27 |
| 12270852 | Method and system for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2025-04-08 |
| 12066484 | Method and device for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2024-08-20 |
| 12025655 | Method and system for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2024-07-02 |
| 11754621 | Method and device for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2023-09-12 |
| 11630149 | Method and system for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2023-04-18 |
| 11448692 | Method and device for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2022-09-20 |
| 11073551 | Method and system for wafer-level testing | Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yinlung Lu | 2021-07-27 |
| 8248091 | Universal array type probe card design for semiconductor device testing | Hsu Ming Cheng, Pi-Huang Lee, Ann Luh, Frank Hwang, Wen-Hung Wu | 2012-08-21 |
| 7781235 | Chip-probing and bumping solutions for stacked dies having through-silicon vias | Wen-Liang Luo, Hsu Ming Cheng | 2010-08-24 |
| 7598523 | Test structures for stacking dies having through-silicon vias | Wen-Liang Luo, Hsu Ming Cheng | 2009-10-06 |