Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6362040 | Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates | Helmut Tews, Brian Lee, Raj Jammy, John Faltermeier | 2002-03-26 |
| 6359299 | Apparatus and method for forming controlled deep trench top isolation layers | — | 2002-03-19 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens | 2002-02-19 |
| 6348388 | Process for fabricating a uniform gate oxide of a vertical transistor | Johnathan E. Faltermeier, Suryanarayan G. Hegde, Rajarao Jammy, Brian Lee, Helmut Tews | 2002-02-19 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens | 2002-01-15 |
| 6331459 | Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAM | — | 2001-12-18 |
| 6327170 | Reducing impact of coupling noise in multi-level bitline architecture | Gerhard Mueller | 2001-12-04 |
| 6323103 | Method for fabricating transistors | Rajesh Rengarajan, Jochen Beintner, Hans-Oliver Joachim | 2001-11-27 |
| 6320780 | Reduced impact from coupling noise in diagonal bitline architectures | Gerhard Mueller | 2001-11-20 |
| 6320215 | Crystal-axis-aligned vertical side wall device | Gary B. Bronner, Jack A. Mandelman, Carl Radens | 2001-11-20 |
| 6319788 | Semiconductor structure and manufacturing methods | Martin Schrems, Carl Radens | 2001-11-20 |
| 6291335 | Locally folded split level bitline wiring | Rainer Florian Schnabel, Thomas Rupp, Gerhard Mueller | 2001-09-18 |
| 6271142 | Process for manufacture of trench DRAM capacitor buried plates | Carl Radens, Dirk Tobben | 2001-08-07 |
| 6265742 | Memory cell structure and fabrication | Jochen Beintner, Hans-Oliver Joachim | 2001-07-24 |
| 6258659 | Embedded vertical DRAM cells and dual workfunction logic gates | Ramachandra Divakaruni, Jack A. Mandelman, Thomas Rupp | 2001-07-10 |
| 6255683 | Dynamic random access memory | Carl Radens, John K. DeBrosse, Jack A. Mandelman | 2001-07-03 |
| 6255158 | Process of manufacturing a vertical dynamic random access memory device | Toshiharu Furukawa, David V. Horak, Jack A. Mandelman, Carl Radens, Thomas Rupp | 2001-07-03 |
| 6229173 | Hybrid 5F2 cell layout for buried surface strap aligned to vertical transistor | Carl Radens | 2001-05-08 |
| 6204140 | Dynamic random access memory | Jochen Beintner, Scott D. Halle, Jack A. Mandelman, Carl Radens, Juergen Wittmann +1 more | 2001-03-20 |
| 6201730 | Sensing of memory cell via a plateline | Johann Alsmeier, Gerhard Mueller, Young Jin Park | 2001-03-13 |
| 6194755 | Low-resistance salicide fill for trench capacitors | Jeffrey P. Gambino, Jack A. Mandelman, Carl Radens | 2001-02-27 |
| 6194736 | Quantum conductive recrystallization barrier layers | Susan E. Chaloux, Tze-Chiang Chen, Johnathan E. Faltermeier, Rajarao Jammy, Jack A. Mandelman +4 more | 2001-02-27 |
| 6190971 | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region | Carl Radens | 2001-02-20 |
| 6188598 | Reducing impact of coupling noise | Gerhard Mueller | 2001-02-13 |
| 6184107 | Capacitor trench-top dielectric for self-aligned device isolation | Rama Divakaruni, Byeong Y. Kim, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2001-02-06 |