Issued Patents All Time
Showing 51–57 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6184091 | Formation of controlled trench top isolation layers for vertical transistors | Jochen Beintner, Dirk Tobben, Gill Yong Lee, Oswald Spindler, Zvonimir Gabric | 2001-02-06 |
| 6177698 | Formation of controlled trench top isolation layers for vertical transistors | Jochen Beintner, Dirk Tobben, Gill Yong Lee, Oswald Spindler, Zvonimir Gabric | 2001-01-23 |
| 6153902 | Vertical DRAM cell with wordline self-aligned to storage trench | Toshiharu Furukawa, David V. Horak, Jack A. Mandelman, Carl Radens, Thomas Rupp | 2000-11-28 |
| 6150670 | Process for fabricating a uniform gate oxide of a vertical transistor | Johnathan E. Faltermeier, Suryanarayan G. Hegde, Rajarao Jammy, Brian Lee, Helmut Tews | 2000-11-21 |
| 6093614 | Memory cell structure and fabrication | Jochen Beintner, Hans-Oliver Joachim | 2000-07-25 |
| 6074909 | Apparatus and method for forming controlled deep trench top isolation layers | — | 2000-06-13 |
| 6013937 | Buffer layer for improving control of layer thickness | Jochen Beintner, Carl Radens | 2000-01-11 |