TS

Theodorus E. Standaert

IBM: 284 patents #82 of 70,183Top 1%
Globalfoundries: 18 patents #182 of 4,424Top 5%
TE Tessera: 10 patents #41 of 271Top 20%
Samsung: 1 patents #49,284 of 75,807Top 70%
AM AMD: 1 patents #5,683 of 9,279Top 65%
SS Stmicroelectronics Sa: 1 patents #938 of 1,676Top 60%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
RE Renesas Electronics: 1 patents #2,739 of 4,529Top 65%
📍 Clifton Park, NY: #2 of 1,126 inventorsTop 1%
🗺 New York: #54 of 115,490 inventorsTop 1%
Overall (All Time): #1,202 of 4,157,543Top 1%
309
Patents All Time

Issued Patents All Time

Showing 201–225 of 309 patents

Patent #TitleCo-InventorsDate
9564437 Method and structure for forming FinFET CMOS with dual doped STI regions Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2017-02-07
9559014 Self-aligned punch through stopper liner for bulk FinFET Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2017-01-31
9558991 Formation of isolation surrounding well implantation Kangguo Cheng, Shom Ponoth, Tenko Yamashita 2017-01-31
9559009 Gate structure cut after formation of epitaxial active regions Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Ruilong Xie 2017-01-31
9553088 Forming semiconductor device with close ground rules Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2017-01-24
9548243 Self aligned via and pillar cut for at least a self aligned double pitch Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner 2017-01-17
9530698 Method and structure for forming FinFET CMOS with dual doped STI regions Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-12-27
9508825 Method and structure for forming gate contact above active area with trench silicide Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-11-29
9508587 Formation of isolation surrounding well implantation Kangguo Cheng, Shom Ponoth, Tenko Yamashita 2016-11-29
9508818 Method and structure for forming gate contact above active area with trench silicide Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-11-29
9490252 MIM capacitor formation in RMG module Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-11-08
9490253 Gate planarity for finFET using dummy polish stop Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-11-08
9484264 Field effect transistor contacts Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-11-01
9478549 FinFET with dielectric isolation by silicon-on-nothing and method of fabrication Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Tenko Yamashita 2016-10-25
9472616 Undercut insulating regions for silicon-on-insulator device Kangguo Cheng, Bruce B. Doris, Balasubramanian Pranatharthiharan, Shom Ponoth, Tenko Yamashita 2016-10-18
9449874 Self-forming barrier for subtractive copper Vamsi K. Paruchuri 2016-09-20
9425184 Electrostatic discharge devices and methods of manufacture Huiming Bu, Junjun Li, Tenko Yamashita 2016-08-23
9418902 Forming isolated fins from a substrate Kangguo Cheng, Shom Ponoth, Balasubramanian Pranatharthiharan, Tenko Yamashita 2016-08-16
9406548 Formation of isolation surrounding well implantation Kangguo Cheng, Shom Ponoth, Tenko Yamashita 2016-08-02
9406665 Integrated passive devices for finFET technologies Thomas N. Adam, Kangguo Cheng, Balasubramanian Pranatharthi Haran, Shom Ponoth, Tenko Yamashita 2016-08-02
9406570 FinFET device Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Tenko Yamashita 2016-08-02
9379057 Method and structure to reduce the electric field in semiconductor wiring interconnects Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Christopher J. Penny 2016-06-28
9373618 Integrated FinFET capacitor Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang 2016-06-21
9373697 Spacer replacement for replacement metal gate semiconductor devices Sanjay C. Mehta, Shom Ponoth, Muthumanickam Sankarapandian, Tenko Yamashita 2016-06-21
9368343 Reduced external resistance finFET device Kangguo Cheng, Shom Ponoth, Raghavasimhan Sreenivasan, Tenko Yamashita 2016-06-14