Issued Patents All Time
Showing 51–75 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9105693 | Microelectronic structure including air gap | Daniel C. Edelstein, David V. Horak, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth +1 more | 2015-08-11 |
| 9089080 | Corrugated interfaces for multilayered interconnects | Lawrence A. Clevenger, Timothy J. Dalton, Sampath Purushothaman, Carl Radens | 2015-07-21 |
| 9064871 | Vertical electronic fuse | Junjing Bao, Yan Li, Dan Moy | 2015-06-23 |
| 9059251 | Microelectronic structure including air gap | Daniel C. Edelstein, David V. Horak, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth +1 more | 2015-06-16 |
| 8871624 | Sealed air gap for semiconductor chip | David V. Horak, Charles W. Koburger, III, Douglas C. La Tulipe, Jr., Shom Ponoth | 2014-10-28 |
| 8841208 | Method of forming vertical electronic fuse interconnect structures including a conductive cap | Junjing Bao, Yan Li, Dan Moy | 2014-09-23 |
| 8828521 | Corrugated interfaces for multilayered interconnects | Lawrence A. Clevenger, Timothy J. Dalton, Sampath Purushothaman, Carl Radens | 2014-09-09 |
| 8828862 | Air-dielectric for subtractive etch line and via metallization | David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang | 2014-09-09 |
| 8809183 | Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer | Griselda Bonilla, Lawrence A. Clevenger, Satyanarayana V. Nitta, Shom Ponoth | 2014-08-19 |
| 8735279 | Air-dielectric for subtractive etch line and via metallization | David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang | 2014-05-27 |
| 8525153 | Structure including voltage controlled negative resistance | Fen Chen, Michael A. Shinosky | 2013-09-03 |
| 8512849 | Corrugated interfaces for multilayered interconnects | Lawrence A. Clevenger, Timothy J. Dalton, Sampath Purushothaman, Carl Radens | 2013-08-20 |
| 8491987 | Selectively coated self-aligned mask | Matthew E. Colburn, Stephen M. Gates, Jeffrey Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman +1 more | 2013-07-23 |
| 8492270 | Structure for nano-scale metallization and method for fabricating same | Shom Ponoth, David V. Horak, Sivananda K. Kanakasabapathy, Charles W. Koburger, III, Chih-Chao Yang | 2013-07-23 |
| 8481423 | Methods to mitigate plasma damage in organosilicate dielectrics | John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Jean-Michel Dubois, Daniel C. Edelstein +8 more | 2013-07-09 |
| 8470706 | Methods to mitigate plasma damage in organosilicate dielectrics | John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Jean-Michel Dubois, Daniel C. Edelstein +8 more | 2013-06-25 |
| 8461678 | Structure with self aligned resist layer on an interconnect surface and method of making same | Daniel C. Edelstein, Robert D. Miller | 2013-06-11 |
| 8421239 | Crenulated wiring structure and method for integrated circuit interconnects | Griselda Bonilla, Satyanarayana V. Nitta, Shom Ponoth | 2013-04-16 |
| 8390079 | Sealed air gap for semiconductor chip | David V. Horak, Charles W. Koburger, III, Douglas C. La Tulipe, Jr., Shom Ponoth | 2013-03-05 |
| 8343868 | Device and methodology for reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2013-01-01 |
| 8338952 | Interconnect structures with ternary patterned features generated from two lithographic processes | Matthew E. Colburn, Satyanarayana V. Nitta, Sampath Purushothaman | 2012-12-25 |
| 8298937 | Interconnect structure fabricated without dry plasma etch processing | Maxime Darnon, Jeffrey P. Gambino, Qinghuang Lin | 2012-10-30 |
| 8288268 | Microelectronic structure including air gap | Daniel C. Edelstein, David V. Horak, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth +1 more | 2012-10-16 |
| 8232618 | Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach | Gregory Breyta, David V. Horak, Charles W. Koburger, III, Douglas C. La Tulipe, Jr., Shom Ponoth | 2012-07-31 |
| 8227336 | Structure with self aligned resist layer on an interconnect surface and method of making same | Daniel C. Edelstein, Robert D. Miller | 2012-07-24 |