Issued Patents All Time
Showing 101–125 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6563173 | Silicon-on-insulator chip having an isolation barrier for reliability | Ronald J. Bolam, Subhash B. Kulkarni | 2003-05-13 |
| 6541317 | Polysilicon doped transistor | K. Paul Muller, Ghavam G. Shahidi | 2003-04-01 |
| 6531375 | Method of forming a body contact using BOX modification | Kenneth J. Giewont, Eric Adler, Neena Garg, Michael Hargrove, Charles W. Koburger, III +2 more | 2003-03-11 |
| 6521947 | Method of integrating substrate contact on SOI wafers with STI process | Atul Ajmera, Effendi Leobandung, Werner Rausch, Ghavam G. Shahidi | 2003-02-18 |
| 6506649 | Method for forming notch gate having self-aligned raised source/drain structure | Ka-Hing Fung, Atul Ajmera, Victor Ku | 2003-01-14 |
| 6492684 | Silicon-on-insulator chip having an isolation barrier for reliability | Ronald J. Bolam, Subhash B. Kulkarni | 2002-12-10 |
| 6451634 | Method of fabricating a multistack 3-dimensional high density semiconductor device | William H. Ma | 2002-09-17 |
| 6440807 | Surface engineering to prevent EPI growth on gate poly during selective EPI processing | Atul Ajmera, Michael D. Steigerwalt | 2002-08-27 |
| 6437377 | Low dielectric constant sidewall spacer using notch gate process | Atul Ajmera, Ka-Hing Fung, Victor Ku | 2002-08-20 |
| 6429084 | MOS transistors with raised sources and drains | Heemyong Park, Fariborz Assaderaghi | 2002-08-06 |
| 6429488 | Densely patterned silicon-on-insulator (SOI) region on a wafer | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2002-08-06 |
| 6404014 | Planar and densely patterned silicon-on-insulator structure | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2002-06-11 |
| 6395587 | Fully amorphized source/drain for leaky junctions | Scott W. Crowder, Melanie J. Sherony | 2002-05-28 |
| 6387742 | Thermal conductivity enhanced semiconductor structures and fabrication processes | Robert J. Gauthier, Jr., William R. Tonti, Steven H. Voldman | 2002-05-14 |
| 6352905 | Method and structure of high and low K buried oxide for SOI technology | Robert J. Gauthier, Jr., Steven H. Voldman | 2002-03-05 |
| 6339005 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET | Andres Bryant, Jerome B. Lasky, Effendi Leobandung | 2002-01-15 |
| 6291858 | Multistack 3-dimensional high density semiconductor device and method for fabrication | William H. Ma | 2001-09-18 |
| 6288426 | Thermal conductivity enhanced semiconductor structures and fabrication processes | Robert J. Gauthier, Jr., William R. Tonti, Steven H. Voldman | 2001-09-11 |
| 6281095 | Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability | Ronald J. Bolam, Subhash B. Kulkarni | 2001-08-28 |
| 6255145 | Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product | Atul Ajmera, Devendra K. Sadana | 2001-07-03 |
| 6214694 | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2001-04-10 |
| 6180486 | Process of fabricating planar and densely patterned silicon-on-insulator structure | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2001-01-30 |
| 6166420 | Method and structure of high and low K buried oxide for SoI technology | Robert J. Gauthier, Jr., Steven H. Voldman | 2000-12-26 |
| 6133610 | Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture | Ronald J. Bolam, Subhash B. Kulkarni | 2000-10-17 |
| 5811357 | Process of etching an oxide layer | Michael D. Armacost, Tina Wagner, Michael L. Passow, Matthew Sendelbach, William C. Wille | 1998-09-22 |