Issued Patents All Time
Showing 76–100 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7759213 | Pattern independent Si:C selective epitaxy | Abhishek Dube, Ashima B. Chakravarti | 2010-07-20 |
| 7682915 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance | Huajie Chen, Judson R. Holt, Kern Rim | 2010-03-23 |
| 7622341 | Sige channel epitaxial development for high-k PFET manufacturability | Michael P. Chudzik, Linda Black | 2009-11-24 |
| 7544994 | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure | Huilong Zhu | 2009-06-09 |
| 7446005 | Manufacturable recessed strained RSD structure and process for advanced CMOS | Brian W. Messenger, Renee T. Mo | 2008-11-04 |
| 7446350 | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer | Huajie Chen, Dureseti Chidambarrao, Henry K. Utomo | 2008-11-04 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance | Huajie Chen, Judson R. Holt, Kern Rim | 2008-06-03 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability | Ronald J. Bolam, Subhash B. Kulkami | 2008-05-27 |
| 7348633 | Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions | Junedong Lee, Devendra K. Sadana, Ghavam G. Shahidi | 2008-03-25 |
| 7183573 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet | Andres Bryant, Jerome B. Lasky, Effendi Leobandung | 2007-02-27 |
| 7166521 | SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer | Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Leathen Shi | 2007-01-23 |
| 7163866 | SOI MOSFETS exhibiting reduced floating-body effects | Fariborz Assaderaghi, Werner Rausch, Ghavam G. Shahidi | 2007-01-16 |
| 7115463 | Patterning SOI with silicon mask to create box at different depths | Devendra K. Sadana, Michael D. Steigerwalt | 2006-10-03 |
| 7115955 | Semiconductor device having a strained raised source/drain | Brian W. Messenger, Renee T. Mo | 2006-10-03 |
| 6900092 | Surface engineering to prevent epi growth on gate poly during selective epi processing | Atul Ajmera, Michael D. Steigerwalt | 2005-05-31 |
| 6891228 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Byoung Hun Lee, Paul D. Agnello, Ghavam G. Shahidi | 2005-05-10 |
| 6884667 | Field effect transistor with stressed channel and method for making same | Bruce B. Doris, Dureseti Chidambarrao, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana | 2005-04-26 |
| 6835633 | SOI wafers with 30-100 å buried oxide (BOX) created by wafer bonding using 30-100 å thin oxide as bonding layer | Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Leathen Shi | 2004-12-28 |
| 6828630 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Byoung Hun Lee, Paul D. Agnello, Ghavam G. Shahidi | 2004-12-07 |
| 6808974 | CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions | Heemyong Park, Fariborz Assaderaghi | 2004-10-26 |
| 6717216 | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device | Bruce B. Doris, Dureseti Chidambarrao, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana | 2004-04-06 |
| 6686629 | SOI MOSFETS exhibiting reduced floating-body effects | Fariborz Assaderaghi, Werner Rausch, Ghavam G. Shahidi | 2004-02-03 |
| 6645795 | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator | K. Paul Muller, Ghavam G. Shahidi | 2003-11-11 |
| 6602759 | Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon | Atul Ajmera, Klaus D. Beyer | 2003-08-05 |
| 6599813 | Method of forming shallow trench isolation for thin silicon-on-insulator substrates | Klaus D. Beyer | 2003-07-29 |