Issued Patents All Time
Showing 51–75 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7235847 | Semiconductor device having a gate with a thin conductive layer | Sinan Goktepeli, Alexander Demkov | 2007-06-26 |
| 7226833 | Semiconductor device structure and method therefor | Ted R. White, Alexander L. Barr, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean | 2007-06-05 |
| 7221006 | GeSOI transistor with low junction current and low junction capacitance and method for making the same | Sinan Goktepeli, Chun-Li Liu | 2007-05-22 |
| 7217667 | Processes for forming electronic devices including a semiconductor layer | Victor H. Vartanian | 2007-05-15 |
| 7205202 | Semiconductor device and method for regional stress control | Vance H. Adams | 2007-04-17 |
| 7202117 | Method of making a planar double-gated transistor | — | 2007-04-10 |
| 7195963 | Method for making a semiconductor structure using silicon germanium | Chun-Li Liu, Choh Fei Yeap | 2007-03-27 |
| 7166897 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device | Vance H. Adams, Chun-Li Liu, Brian A. Winstead | 2007-01-23 |
| 7163903 | Method for making a semiconductor structure using silicon germanium | Alexander L. Barr, Mariam Sadaka, Ted R. White | 2007-01-16 |
| 7135379 | Isolation trench perimeter implant for threshold voltage control | James D. Burnett | 2006-11-14 |
| 7112832 | Transistor having multiple channels | Leo Mathew | 2006-09-26 |
| 7105430 | Method for forming a semiconductor device having a notched control electrode and structure thereof | James D. Burnett | 2006-09-12 |
| 7045432 | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) | Olubunmi O. Adetutu, Alexander L. Barr | 2006-05-16 |
| 7037795 | Low RC product transistors in SOI semiconductor process | Alexander L. Barr, Olubunmi O. Adetutu, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean +1 more | 2006-05-02 |
| 7029980 | Method of manufacturing SOI template layer | Chun-Li Liu, Matthew W. Stoker, Philip J. Tobin, Mariam Sadaka, Alexander L. Barr +4 more | 2006-04-18 |
| 6964911 | Method for forming a semiconductor device having isolation regions | Alexander L. Barr | 2005-11-15 |
| 6921700 | Method of forming a transistor having multiple channels | Leo Mathew | 2005-07-26 |
| 6831350 | Semiconductor structure with different lattice constant materials and method for forming the same | Chun-Li Liu, Alexander L. Barr, John M. Grant, Bich-Yen Nguyen, Tab A. Stephens +2 more | 2004-12-14 |
| 6573160 | Method of recrystallizing an amorphous region of a semiconductor | William J. Taylor, Jr., David C. Gilmer, Prasad Alluri, Christopher C. Hobbs, Michael Rendon +1 more | 2003-06-03 |
| 6433382 | Split-gate vertically oriented EEPROM device and process | Kuo-Tung Chang, Keith E. Witek, Jon T. Fitch | 2002-08-13 |
| 5985736 | Process for forming field isolation | Karl Wimmer | 1999-11-16 |
| 5741736 | Process for forming a transistor with a nonuniformly doped channel | Frank K. Baker, Jr. | 1998-04-21 |
| 5705415 | Process for forming an electrically programmable read-only memory cell | Ko-Min Chang | 1998-01-06 |
| 5605855 | Process for fabricating a graded-channel MOS device | Ko-Min Chang, Craig T. Swift, Shih-Wei Sun, Shiang-Chyong Luo | 1997-02-25 |
| 5567958 | High-performance thin-film transistor and SRAM memory cell | James D. Hayden, Bich-Yen Nguyen | 1996-10-22 |