Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6433382 | Split-gate vertically oriented EEPROM device and process | Marius Orlowski, Kuo-Tung Chang, Jon T. Fitch | 2002-08-13 |
| 6146970 | Capped shallow trench isolation and method of formation | Mike Chen, Stephen S. Poon | 2000-11-14 |
| 6037202 | Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase | — | 2000-03-14 |
| 5949706 | Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line | Ko-Min Chang, Bruce L. Morton, Clinton C. K. Kuo, Kent J. Cooper | 1999-09-07 |
| 5898619 | Memory cell having a plural transistor transmission gate and method of formation | Ko-Min Chang, Bruce L. Morton, Clinton C. K. Kuo, Kent J. Cooper | 1999-04-27 |
| 5886382 | Trench transistor structure comprising at least two vertical transistors | — | 1999-03-23 |
| 5879971 | Trench random access memory cell and method of formation | — | 1999-03-09 |
| 5712208 | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants | Hsing-Huang Tseng, Philip J. Tobin | 1998-01-27 |
| 5705409 | Method for forming trench transistor structure | — | 1998-01-06 |
| 5627395 | Vertical transistor structure | Jon T. Fitch, Carlos Mazure | 1997-05-06 |
| 5612563 | Vertically stacked vertical transistors used to form vertical logic gate structures | Jon T. Fitch, Carlos Mazure | 1997-03-18 |
| 5578850 | Vertically oriented DRAM structure | Jon T. Fitch, Carlos Mazure | 1996-11-26 |
| 5554870 | Integrated circuit having both vertical and horizontal devices and process for making the same | Jon T. Fitch, Suresh Venkatesan | 1996-09-10 |
| 5527723 | Method for forming a dynamic contact which can be either on or off or switched therebetween | Jon T. Fitch, Carlos Mazure | 1996-06-18 |
| 5510645 | Semiconductor structure having an air region and method of forming the semiconductor structure | Jon T. Fitch, Papu D. Maniar, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria | 1996-04-23 |
| 5461488 | Computerized facsimile (FAX) system and method of operation | — | 1995-10-24 |
| 5451538 | Method for forming a vertically integrated dynamic memory cell | Jon T. Fitch, Carlos Mazure | 1995-09-19 |
| 5414288 | Vertical transistor having an underlying gate electrode contact | Jon T. Fitch, Carlos Mazure | 1995-05-09 |
| 5414289 | Dynamic memory device having a vertical transistor | Jon T. Fitch, Carlos Mazure | 1995-05-09 |
| 5398200 | Vertically formed semiconductor random access memory device | Carlos Mazure, Jon T. Fitch, James D. Hayden | 1995-03-14 |
| 5393681 | Method for forming a compact transistor structure | Jon T. Fitch, Carlos Mazure | 1995-02-28 |
| 5376562 | Method for forming vertical transistor structures having bipolar and MOS devices | Jon T. Fitch, Carlos Mazure, James D. Hayden | 1994-12-27 |
| 5340754 | Method for forming a transistor having a dynamic connection between a substrate and a channel region | Jon T. Fitch, Carlos Mazure | 1994-08-23 |
| 5324673 | Method of formation of vertical transistor | Jon T. Fitch, Carlos Mazure | 1994-06-28 |
| 5324683 | Method of forming a semiconductor structure having an air region | Jon T. Fitch, Papu D. Maniar, Jerry Gelatos, Reza Moazzami, Sergio A. Ajuria | 1994-06-28 |