Issued Patents All Time
Showing 26–50 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7608893 | Multi-channel transistor structure and method of making thereof | — | 2009-10-27 |
| 7592248 | Method of forming semiconductor device having nanotube structures | Peter L. G. Ventzek | 2009-09-22 |
| 7575958 | Programmable fuse with silicon germanium | Alexander B. Hoefler | 2009-08-18 |
| 7544576 | Diffusion barrier for nickel silicides in a semiconductor fabrication process | Dharmesh Jawarani, Chun-Li Liu | 2009-06-09 |
| 7535060 | Charge storage structure formation in transistor with vertical channel region | — | 2009-05-19 |
| 7517741 | Single transistor memory cell with reduced recombination rates | James D. Burnett | 2009-04-14 |
| 7510956 | MOS device with multi-layer gate stack | Chun-Li Liu, Matthew W. Stoker | 2009-03-31 |
| 7456055 | Process for forming an electronic device including semiconductor fins | Suresh Venkatesan | 2008-11-25 |
| 7442621 | Semiconductor process for forming stress absorbent shallow trench isolation structures | Mark C. Foisy, Olubunmi O. Adetutu | 2008-10-28 |
| 7442590 | Method for forming a semiconductor device having a fin and structure thereof | — | 2008-10-28 |
| 7435639 | Dual surface SOI by lateral epitaxial overgrowth | Brian A. Winstead, Omar Zia, Mariam Sadaka | 2008-10-14 |
| 7402476 | Method for forming an electronic device | Brian J. Goolsby | 2008-07-22 |
| 7371677 | Laterally grown nanotubes and method of formation | Shahid Rauf, Peter L. G. Ventzek | 2008-05-13 |
| 7364970 | Method of making a multi-bit non-volatile memory (NVM) cell and structure | Sinan Goktepeli | 2008-04-29 |
| 7354831 | Multi-channel transistor structure and method of making thereof | — | 2008-04-08 |
| 7354814 | Semiconductor process with first transistor types oriented in a first plane and second transistor types oriented in a second plane | Bich-Yen Nguyen | 2008-04-08 |
| 7339241 | FinFET structure with contacts | Tab A. Stephens | 2008-03-04 |
| 7312129 | Method for producing two gates controlling the same channel | Sinan Goktepeli, Alexander B. Hoefler | 2007-12-25 |
| 7291521 | Self correcting suppression of threshold voltage variation in fully depleted transistors | Yasuhito Shiho | 2007-11-06 |
| 7288448 | Method and apparatus for mobility enhancement in a semiconductor device | Suresh Venkatesan | 2007-10-30 |
| 7279433 | Deposition and patterning of boron nitride nanotube ILD | Peter L. G. Ventzek, Kurt H. Junker | 2007-10-09 |
| 7271069 | Semiconductor device having a plurality of different layers and method therefor | Vance H. Adams | 2007-09-18 |
| 7256077 | Method for removing a semiconductor layer | — | 2007-08-14 |
| 7238555 | Single transistor memory cell with reduced programming voltages | James D. Burnett | 2007-07-03 |
| 7238580 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration | Vance H. Adams, Chun-Li Liu, Matthew W. Stoker | 2007-07-03 |