Issued Patents All Time
Showing 1–25 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12322472 | Voltage generation circuit for SRAM | Hubert M. Bode, Glenn C. Abeln | 2025-06-03 |
| 12181522 | Integrated circuit having test circuitry for memory sub-systems | Jeffrey Stump | 2024-12-31 |
| 11233663 | Physically unclonable function having source bias transistors | Glenn C. Abeln, Brad J. Garni, Nihaar N. Mahatme | 2022-01-25 |
| 11056161 | Data processing system and method for generating a digital code with a physically unclonable function | Nihaar N. Mahatme, Brad J. Garni | 2021-07-06 |
| 10574469 | Physically unclonable function and method for generating a digital code | Brad J. Garni, Nihaar N. Mahatme | 2020-02-25 |
| 10446225 | Memory system having a source bias circuit | Nihaar N. Mahatme | 2019-10-15 |
| 10417104 | Data processing system with built-in self-test and method therefor | Colin MacDonald, Jose A. Lyon, Chris P. Nappi, Andrew Payne | 2019-09-17 |
| 10127998 | Memory having one time programmable (OTP) elements and a method of programming the memory | Thomas E. Tkacik | 2018-11-13 |
| 9947391 | SRAM based physically unclonable function and method for generating a PUF response | Nihaar N. Mahatme, Srikanth Jagannathan | 2018-04-17 |
| 9691451 | Write assist circuit and method therefor | Scott I. Remington | 2017-06-27 |
| 9425775 | Low swing flip-flop with reduced leakage slave latch | Anis M. Jarrar, John M. Dalbey, Colin MacDonald | 2016-08-23 |
| 9407263 | Method and apparatus for a tunable driver circuit | Hector Sanchez | 2016-08-02 |
| 9264040 | Low leakage CMOS cell with low voltage swing | Savithri Sundareswaran, Benjamin Huang, Anis M. Jarrar | 2016-02-16 |
| 9263152 | Address fault detection circuit | Scott I. Remington, Shayan Zhang | 2016-02-16 |
| 9136845 | Level shifter with improved operation | Sayeed A. Badrudduza | 2015-09-15 |
| 9117534 | Fuse circuit with test mode | — | 2015-08-25 |
| 8659322 | Memory having a latching sense amplifier resistant to negative bias temperature instability and method therefor | James D. Burnett, Scott I. Remington | 2014-02-25 |
| 8379468 | Word line fault detection | Ravindraraj Ramaraju | 2013-02-19 |
| 8380768 | Random number generator | — | 2013-02-19 |
| 8254186 | Circuit for verifying the write enable of a one time programmable memory | Mohamed S. Moosa | 2012-08-28 |
| 7824988 | Method of forming an integrated circuit | James D. Burnett, Lawrence N. Herr | 2010-11-02 |
| 7804701 | Method of programming a memory having electrically programmable fuses | — | 2010-09-28 |
| 7787323 | Level detect circuit | Lawrence N. Herr | 2010-08-31 |
| 7733711 | Circuit and method for optimizing memory sense amplifier timing | James D. Burnett | 2010-06-08 |
| 7678620 | Antifuse one time programmable memory array and method of manufacture | — | 2010-03-16 |