Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6849481 | Thyristor-based SRAM and method for the fabrication thereof | Elgin Quek, Pradeep Ramachandramurthy Yelehanka, Tommy Lai, Weining Li | 2005-02-01 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2005-01-11 |
| 6830971 | High K artificial lattices for capacitor applications to use in CU or AL BEOL | Subramanian Balakumar, Chew Hoe Ang, Paul Proctor | 2004-12-14 |
| 6828082 | Method to pattern small features by using a re-flowable hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2004-12-07 |
| 6821904 | Method of blocking nitrogen from thick gate oxide during dual gate CMP | Yelehanka Ramachandramurthy Pradeep, Sanford Chu, Chit Hwei Ng, Purakh Raj Verma | 2004-11-23 |
| 6780691 | Method to fabricate elevated source/drain transistor with large area for silicidation | Randall Cher Liang Cha, Yeow Kheng Lim, Alex See | 2004-08-24 |
| 6762085 | Method of forming a high performance and low cost CMOS device | Soh Yun Siah, Liang-Choo Hsia, Eng Hua Lim, Simon Chooi, Chew Hoe Ang | 2004-07-13 |
| 6747314 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy +2 more | 2004-06-08 |
| 6743291 | Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth | Chew Hoe Ang, Wenhe Lin | 2004-06-01 |
| 6734082 | Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape | Soh Yun Siah, Chew Hoe Ang | 2004-05-11 |
| 6716693 | Method of forming a surface coating layer within an opening within a body by atomic layer deposition | Lap Chan, Sanford Chu, Chit Hwei Ng, Yelehanka Ramachandramurthy Pradeep | 2004-04-06 |
| 6709912 | Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization | Chew Hoe Ang, Jeffrey Chee Wei-Lun, Wenhe Lin | 2004-03-23 |
| 6709934 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek +2 more | 2004-03-23 |
| 6670248 | Triple gate oxide process with high-k gate dielectric | Chew Hoe Ang, Wenhe Lin | 2003-12-30 |
| 6664156 | Method for forming L-shaped spacers with precise width control | Chew Hoe Ang, Eng Hua Lim, Wenhe Lin | 2003-12-16 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-12-16 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-10-14 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6608362 | Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components | Shao Kai, Sanford Chu, Chit Hwei Ng, Sia Choon Beng, Chew Kok Wai | 2003-08-19 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Elgin Quek, Mei Sheng Zhou | 2003-08-12 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding | Soh Yun Siah, Liang-Choo Hsia, Chew Hoe Ang | 2003-07-01 |
| 6566208 | Method to form elevated source/drain using poly spacer | Yang Pan, Lee Yong Meng, Leung Keung, Yelehanka Ramachandramurthy Pradeep, Lap Chan +2 more | 2003-05-20 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2003-04-08 |
| 6544824 | Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel | Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2003-04-08 |