Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6541327 | Method to form self-aligned source/drain CMOS device on insulated staircase oxide | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2003-04-01 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yang Pan, Yong Meng Lee, Ying-Keung Leung +2 more | 2003-01-28 |
| 6468877 | Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner | Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-22 |
| 6468851 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Elgin Quek, Mei Sheng Zhou +1 more | 2002-10-22 |
| 6461887 | Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth | Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan +2 more | 2002-10-08 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-10-08 |
| 6455377 | Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-09-24 |
| 6440800 | Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek +2 more | 2002-08-27 |
| 6436774 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek +2 more | 2002-08-20 |
| 6436770 | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2002-08-20 |
| 6429109 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Elgin Quek, Mei Sheng Zhou, Daniel Yen, Chew Hoe Ang, Eng Hua Lim +1 more | 2002-08-06 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-07-09 |
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek +2 more | 2002-06-18 |
| 6403425 | Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide | Chew Hoe Ang, Wenhe Lin | 2002-06-11 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Elgin Quek, Ravi Sundaresan, Yang Pan, James Lee Yong Meng, Ying Keung +2 more | 2002-06-11 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2002-04-30 |
| 6313008 | Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2001-11-06 |
| 6306715 | Method to form smaller channel with CMOS device by isotropic etching of the gate materials | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee +2 more | 2001-10-23 |
| 6306714 | Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide | Yang Pan, James Yongmeng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan +2 more | 2001-10-23 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP | Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Lap Chan +2 more | 2001-10-16 |
| 6300177 | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2001-10-09 |
| 6268251 | Method of forming MOS/CMOS devices with dual or triple gate oxide | Dong Zhong | 2001-07-31 |
| 6235591 | Method to form gate oxides of different thicknesses on a silicon substrate | Narayanan Balasubramanian, Yelehanka Ramachandamurthy Pradeep, Alan Cuthbertson | 2001-05-22 |
| 6207554 | Gap filling process in integrated circuits using low dielectric constant materials | Yi Xu, Jane Hui, Charles Lin, Yih-Shung Lin | 2001-03-27 |