Issued Patents All Time
Showing 26–50 of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7220642 | Protection of active layers of memory cells during processing of other elements | Igor Sokolik, Suzette K. Pangrle, Nicholas H. Tripsas, Jeffrey A. Shields | 2007-05-22 |
| 7157795 | Composite tantalum nitride/tantalum copper capping layer | Darrell M. Erb, Christy Mei-Chu Woo | 2007-01-02 |
| 7148144 | Method of forming copper sulfide layer over substrate | — | 2006-12-12 |
| 7141482 | Method of making a memory cell | — | 2006-11-28 |
| 7129133 | Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film | Minh Quoc Tran | 2006-10-31 |
| 7084062 | Use of Ta-capped metal line to improve formation of memory element films | Amit P. Marathe | 2006-08-01 |
| 7071564 | Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration | Darrell M. Erb, Christy Mei-Chu Woo | 2006-07-04 |
| 7035141 | Diode array architecture for addressing nanoscale resistive memory arrays | Nicholas H. Tripsas, Colin S. Bill, Michael VanBuskirk, Matthew S. Buynoski, Tzu-Ning Fang +2 more | 2006-04-25 |
| 7011762 | Metal bridging monitor for etch and CMP endpoint detection | Christopher F. Lyons, Ramkumar Subramanian | 2006-03-14 |
| 6989604 | Conformal barrier liner in an integrated circuit interconnect | Christy Mei-Chu Woo, Minh Van Ngo, John Sanchez | 2006-01-24 |
| 6979903 | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | Pin-Chin Connie Wang, Minh Van Ngo | 2005-12-27 |
| 6934032 | Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process | Ramkumar Subramanian, Bharath Rangarajan, Bhanwar Singh | 2005-08-23 |
| 6841473 | Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap | Pin-Chin Connie Wang | 2005-01-11 |
| 6836017 | Protection of low-k ILD during damascene processing with thin liner | Minh Van Ngo, Christy Mei-Chu Woo, John Sanchez, Suzette K. Pangrle | 2004-12-28 |
| 6808591 | Model based metal overetch control | Khoi A. Phan, Bharath Rangarajan, Christopher F. Lyons, Ramkumar Subramanian, Bhanwar Singh +1 more | 2004-10-26 |
| 6771356 | Scatterometry of grating structures to monitor wafer stress | Christopher F. Lyons, Bhanwar Singh, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian +1 more | 2004-08-03 |
| 6756306 | Low temperature dielectric deposition to improve copper electromigration performance | Darrell M. Erb | 2004-06-29 |
| 6723635 | Protection low-k ILD during damascene processing with thin liner | Minh Van Ngo, Christy Mei-Chu Woo, John Sanchez, Suzette K. Pangrle | 2004-04-20 |
| 6720264 | Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties | Kashmir Sahota, Diana M. Schonauer, Johannes Groschopf, Gerd Marxsen | 2004-04-13 |
| 6702648 | Use of scatterometry/reflectometry to measure thin film delamination during CMP | Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian | 2004-03-09 |
| 6699785 | Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects | Kai Yang, Kashmir Sahota | 2004-03-02 |
| 6682978 | Integrated circuit having increased gate coupling capacitance | Stephen Keetai Park | 2004-01-27 |
| 6684172 | Sensor to predict void free films using various grating structures and characterize fill performance | Ramkumar Subramanian, Christopher F. Lyons, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh +1 more | 2004-01-27 |
| 6657303 | Integrated circuit with low solubility metal-conductor interconnect cap | Pin-Chin Connie Wang | 2003-12-02 |
| 6657304 | Conformal barrier liner in an integrated circuit interconnect | Christy Mei-Chu Woo, Minh Van Ngo, John Sanchez | 2003-12-02 |