Issued Patents All Time
Showing 26–50 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7572705 | Semiconductor device and method of manufacturing a semiconductor device | Paul R. Besser | 2009-08-11 |
| 7553732 | Integration scheme for constrained SEG growth on poly during raised S/D processing | David E. Brown | 2009-06-30 |
| 7521380 | Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors | Andrew Waite, Frank (Bin) Yang | 2009-04-21 |
| 7504301 | Stressed field effect transistor and methods for its fabrication | Andrew Waite | 2009-03-17 |
| 7442601 | Stress enhanced CMOS circuits and methods for their fabrication | Gen Pei, Johannes M. van Meer | 2008-10-28 |
| 7402485 | Method of forming a semiconductor device | William G. En, Thorsten Kammler, Eric N. Paton | 2008-07-22 |
| 7279389 | Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning | Karla Romero, Thorsten Kammler, Hans Van Meer | 2007-10-09 |
| 7241700 | Methods for post offset spacer clean for improved selective epitaxy silicon growth | William G. En, Eric N. Paton | 2007-07-10 |
| 7223662 | Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface | Thorsten Kammler, Linda Black | 2007-05-29 |
| 7183169 | Method and arrangement for reducing source/drain resistance with epitaxial growth | Andrew Waite, Philip A. Fisher | 2007-02-27 |
| 7176110 | Technique for forming transistors having raised drain and source regions with different heights | Ralf van Bentum, Thorsten Kammler | 2007-02-13 |
| 7144786 | Technique for forming a transistor having raised drain and source regions with a reduced number of process steps | Ralf van Bentum, Thorsten Kammler | 2006-12-05 |
| 7138320 | Advanced technique for forming a transistor having raised drain and source regions | Ralf van Bentum, Andy Wei | 2006-11-21 |
| 7087509 | Method of forming a gate electrode on a semiconductor device and a device incorporating same | William R. Roche, David Wu, Massud Aminpur | 2006-08-08 |
| 6972478 | Integrated circuit and method for its manufacture | Andrew Waite | 2005-12-06 |
| 6949436 | Composite spacer liner for improved transistor performance | James F. Buller, David Wu, Derick J. Wristers, Daniel Kadosh | 2005-09-27 |
| 6821853 | Differential implant oxide process | James F. Buller | 2004-11-23 |
| 6806126 | Method of manufacturing a semiconductor component | Karsten Wieczorek, Thorsten Kammler | 2004-10-19 |
| 6787464 | Method of forming silicide layers over a plurality of semiconductor devices | Jon D. Cheek | 2004-09-07 |
| 6777281 | Maintaining LDD series resistance of MOS transistors by retarding dopant segregation | Daniel Kadosh, Akif Sultan, David Wu | 2004-08-17 |
| 6743685 | Semiconductor device and method for lowering miller capacitance for high-speed microprocessors | David Wu, Michael Duane | 2004-06-01 |
| 6727558 | Channel isolation using dielectric isolation structures | Michael Duane, David Wu, Massud Aminpur | 2004-04-27 |
| 6642134 | Semiconductor processing employing a semiconductor spacer | Emi Ishida | 2003-11-04 |
| 6624035 | Method of forming a hard mask for halo implants | David Wu, Massud Aminpur | 2003-09-23 |
| 6617219 | Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors | Michael Duane, David Wu, Massud Aminpur | 2003-09-09 |