Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6589847 | Tilted counter-doped implant to sharpen halo profile | Daniel Kadosh, Derick J. Wristers | 2003-07-08 |
| 6569606 | Method of reducing photoresist shadowing during angled implants | David Wu, William R. Roche, Massud Aminpur, Karen L. E. Turnqest | 2003-05-27 |
| 6548335 | Selective epitaxy to reduce gate/gate dielectric interface roughness | Carl Robert Huster, Concetta Riccobene | 2003-04-15 |
| 6506642 | Removable spacer technique | Jon D. Cheek, Daniel Kadosh, James F. Buller, David E. Brown | 2003-01-14 |
| 6482726 | Control trimming of hard mask for sub-100 nanometer transistor gate | Massud Aminpur, David Wu | 2002-11-19 |
| 6440819 | Method for differential trenching in conjunction with differential fieldox growth | — | 2002-08-27 |
| 6410956 | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Vei-Han Chan, Mark Randolph, Nicholas H. Tripsas, Daniel Sobek, Janet Wang +2 more | 2002-06-25 |
| 6391751 | Method for forming vertical profile of polysilicon gate electrodes | David Wu, William R. Roche, Karen L. E. Turnqest | 2002-05-21 |
| 6387755 | Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting | Timothy Thurgate | 2002-05-14 |
| 6372587 | Angled halo implant tailoring using implant mask | Jon D. Cheek, Derick J. Wristers | 2002-04-16 |
| 6355528 | Method to form narrow structure using double-damascene process | Emi Ishida, Tim Thurgate | 2002-03-12 |
| 6351013 | Low-K sub spacer pocket formation for gate capacitance reduction | David Wu, Khanh Tran | 2002-02-26 |
| 6329257 | Method for laterally peaked source doping profiles for better erase control in flash memory devices | Daniel Sobek, Timothy Thurgate | 2001-12-11 |
| 6319804 | Process to separate the doping of polygate and source drain regions in dual gate field effect transistors | David C. Greenlaw | 2001-11-20 |
| 6294433 | Gate re-masking for deeper source/drain co-implantation processes | — | 2001-09-25 |
| 6236596 | Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices | Daniel Sobek, Timothy Thurgate, Vei-Han Chan, Sameer Haddad | 2001-05-22 |
| 6232166 | CMOS processing employing zero degree halo implant for P-channel transistor | Dong-Hyuk Ju | 2001-05-15 |
| 6180468 | Very low thermal budget channel implant process for semiconductors | Bin Yu, Emi Ishida, Timothy Thurgate | 2001-01-30 |
| 6168637 | Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing | Mark Randolph, Timothy Thurgate | 2001-01-02 |
| 6153487 | Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects | Timothy Thurgate, Daniel Sobek, Nicholas H. Tripsas | 2000-11-28 |
| 6127222 | Non-self-aligned side channel implants for flash memory cells | Mark Randolph | 2000-10-03 |
| 6117719 | Oxide spacers as solid sources for gallium dopant introduction | Emi Ishida | 2000-09-12 |
| 6114210 | Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime | David Wu | 2000-09-05 |
| 6107149 | CMOS semiconductor device comprising graded junctions with reduced junction capacitance | David Wu | 2000-08-22 |
| 6051473 | Fabrication of raised source-drain transistor devices | Emi Ishida, Dong-Hyuk Ju, Don Draper | 2000-04-18 |