Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6211074 | Methods and arrangements for reducing stress and preventing cracking in a silicide layer | Guarionex Morales | 2001-04-03 |
| 6200913 | Cure process for manufacture of low dielectric constant interlevel dielectric layers | Lu You, Simon S. Chan, John A. Iacoponi, Robin Cheung | 2001-03-13 |
| 6197703 | Apparatus and method for manufacturing semiconductors using low dielectric constant materials | Lu You, Dawn Hopper | 2001-03-06 |
| 6177364 | Integration of low-K SiOF for damascene structure | — | 2001-01-23 |
| 6166427 | Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application | John A. Iacoponi | 2000-12-26 |
| 6136729 | Method for improving semiconductor dielectrics | Dawn Hopper, Lu You | 2000-10-24 |
| 6133619 | Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics | Kashmir Sahota, David Matsumoto, Mark T. Ramsbey, Yu Sun, Judith Quan Rizzuto | 2000-10-17 |
| 6124201 | Method for manufacturing semiconductors with self-aligning vias | Fei Wang, Robin Cheung, Mark S. Chang, Angela T. Hui | 2000-09-26 |
| 6124640 | Scalable and reliable integrated circuit inter-level dielectric | Kashmir Sahota, Hung-Sheng Chen, Yu Sun | 2000-09-26 |
| 6100192 | Method of forming high integrity tungsten silicide thin films | Guarionex Morales | 2000-08-08 |
| 6093635 | High integrity borderless vias with HSQ gap filled patterned conductive layers | Khanh Tran, Simon S. Chan, Lu You | 2000-07-25 |
| 6080639 | Semiconductor device containing P-HDP interdielectric layer | Chi Chang | 2000-06-27 |
| 6060741 | Stacked gate structure for flash memory application | — | 2000-05-09 |
| 6030901 | Photoresist stripping without degrading low dielectric constant materials | Dawn Hopper, Jacques Bertrand, Lu You | 2000-02-29 |
| 6030891 | Vacuum baked HSQ gap fill layer for high integrity borderless vias | Khanh Tran, Guarionex Morales | 2000-02-29 |
| 6011289 | Metal oxide stack for flash memory application | Lewis Shen | 2000-01-04 |
| 5994778 | Surface treatment of low-k SiOF to prevent metal interaction | Guarionex Morales, Simon S. Chan | 1999-11-30 |
| 5888911 | HSQ processing for reduced dielectric constant | Minh Van Ngo, Khanh Tran, Lu You, Jean Y. Yang | 1999-03-30 |
| 5861677 | Low RC interconnection | Lu You, Robin Cheung, Simon S. Chan | 1999-01-19 |
| 5843836 | Tunneling technology for reducing intra-conductive layer capacitance | Robin Cheung, Simon S. Chan | 1998-12-01 |
| 5801095 | Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology | Christy Mei-Chu Woo | 1998-09-01 |
| 5760480 | Low RC interconnection | Lu You, Robin Cheung, Simon S. Chan | 1998-06-02 |
| 5686761 | Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology | Christy Mei-Chu Woo | 1997-11-11 |
| 5674781 | Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application | Robin Cheung, Rajat Rakkhit, Raymond T. Lee | 1997-10-07 |
| 5670828 | Tunneling technology for reducing intra-conductive layer capacitance | Robin Cheung, Simon S. Chan | 1997-09-23 |