Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6642619 | System and method for adhesion improvement at an interface between fluorine doped silicon oxide and tantalum | Minh Van Ngo, Jeremy I. Martin | 2003-11-04 |
| 6613657 | BPSG, SA-CVD liner/P-HDP gap fill | Minh Van Ngo, Wenmei Li, Kelwin Ko, Kuo-Tung Chang, Tyagamohan Gottipati | 2003-09-02 |
| 6607925 | Hard mask removal process including isolation dielectric refill | Unsoon Kim, Yider Wu, Krishnashree Achuthan | 2003-08-19 |
| 6599839 | Plasma etch process for nonhomogenous film | Calvin T. Gabriel, Lynne A. Okada, Suzette K. Pangrle, Fei Wang | 2003-07-29 |
| 6576982 | Use of sion for preventing copper contamination of dielectric layer | Lu You, Minh Van Ngo | 2003-06-10 |
| 6576545 | Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers | Lu You, Minh Van Ngo | 2003-06-10 |
| 6566283 | Silane treatment of low dielectric constant materials in semiconductor device manufacturing | Suzette K. Pangrle, Minh Van Ngo, Lu You | 2003-05-20 |
| 6562416 | Method of forming low resistance vias | Minh Van Ngo, Robert A. Huertas | 2003-05-13 |
| 6530340 | Apparatus for manufacturing planar spin-on films | Lu You, Richard J. Huang | 2003-03-11 |
| 6528432 | H2-or H2/N2-plasma treatment to prevent organic ILD degradation | Minh Van Ngo, Robert A. Huertas | 2003-03-04 |
| 6518646 | Semiconductor device with variable composition low-k inter-layer dielectric and method of making | Suzette K. Pangrle, Calvin T. Gabriel, Richard J. Huang, Lu You | 2003-02-11 |
| 6486029 | Integration of an ion implant hard mask structure into a process for fabricating high density memory cells | David K. Foote, Bharath Rangarajan, Stephan K. Park, Fei Wang, Jack F. Thomas +2 more | 2002-11-26 |
| 6482755 | HDP deposition hillock suppression method in integrated circuits | Minh Van Ngo, Robert A. Huertas | 2002-11-19 |
| 6479898 | Dielectric treatment in integrated circuit interconnects | Minh Van Ngo, Joffre F. Bernard | 2002-11-12 |
| 6459155 | Damascene processing employing low Si-SiON etch stop layer/arc | Ramkumar Subramanian, Minh Van Ngo | 2002-10-01 |
| 6458677 | Process for fabricating an ONO structure | David K. Foote, Bharath Rangarajan | 2002-10-01 |
| 6455409 | Damascene processing using a silicon carbide hard mask | Ramkumar Subramanian | 2002-09-24 |
| 6436808 | NH3/N2-plasma treatment to prevent organic ILD degradation | Minh Van Ngo, Jeremy I. Martin | 2002-08-20 |
| 6436766 | Process for fabricating high density memory cells using a polysilicon hard mask | Bharath Rangarajan, David K. Foote, Fei Wang, Stephen Keetai Park, Jack F. Thomas +2 more | 2002-08-20 |
| 6429121 | Method of fabricating dual damascene with silicon carbide via mask/ARC | Ramkumar Subramanian, Richard J. Huang | 2002-08-06 |
| 6429141 | Method of manufacturing a semiconductor device with improved line width accuracy | Minh Van Ngo, Bhanwar Singh, Carmen Morales | 2002-08-06 |
| 6420278 | Method for improving the dielectric constant of silicon-based semiconductor materials | Richard J. Huang, Lu You | 2002-07-16 |
| 6410458 | Method and system for eliminating voids in a semiconductor device | Lu You, John Jianshi Wang | 2002-06-25 |
| 6407009 | Methods of manufacture of uniform spin-on films | Lu You, Richard J. Huang | 2002-06-18 |
| 6406960 | Process for fabricating an ONO structure having a silicon-rich silicon nitride layer | David K. Foote, Bharath Rangarajan, Arvind Halliyal | 2002-06-18 |