Issued Patents All Time
Showing 51–75 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6654659 | Quartz crystal monitor wafer for lithography and etch process monitoring | Cyrus E. Tabery | 2003-11-25 |
| 6635409 | Method of strengthening photoresist to prevent pattern collapse | Scott A. Bell, Todd P. Lukanc, Marina V. Plat | 2003-10-21 |
| 6627360 | Carbonization process for an etch mask | Scott A. Bell | 2003-09-30 |
| 6624642 | Metal bridging monitor for etch and CMP endpoint detection | Ramkumar Subramanian, Steven C. Avanzino | 2003-09-23 |
| 6623893 | Pellicle for use in EUV lithography and a method of making such a pellicle | Harry J. Levinson | 2003-09-23 |
| 6605855 | CVD plasma process to fill contact hole in damascene process | Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Sanjay K. Yedur, Ramkumar Subramanian | 2003-08-12 |
| 6605413 | Chemical treatment to strengthen photoresists to prevent pattern collapse | Ramkumar Subramanian | 2003-08-12 |
| 6605546 | Dual bake for BARC fill without voids | Ramkumar Subramanian, Wolfram Grundke, Bhanwar Singh, Marina V. Plat | 2003-08-12 |
| 6599810 | Shallow trench isolation formation with ion implantation | Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok | 2003-07-29 |
| 6593035 | Pellicle for use in small wavelength lithography and a method for making such a pellicle using polymer films | Harry J. Levinson | 2003-07-15 |
| 6589711 | Dual inlaid process using a bilayer resist | Ramkumar Subramanian, Marina V. Plat, Bhanwar Singh | 2003-07-08 |
| 6566214 | Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer | Ramkumar Subramanian, Scott A. Bell, Todd P. Lukanc, Marina V. Plat | 2003-05-20 |
| 6563221 | Connection structures for integrated circuits and processes for their formation | Scott A. Bell, Todd P. Lukanc, Marina V. Plat, Ramkumar Subramanian | 2003-05-13 |
| 6558965 | Measuring BARC thickness using scatterometry | Bhanwar Singh, Ramkumar Subramanian, Marina V. Plat | 2003-05-06 |
| 6548423 | Multilayer anti-reflective coating process for integrated circuit fabrication | Marina V. Plat, Scott A. Bell, Todd P. Lukanc | 2003-04-15 |
| 6544885 | Polished hard mask process for conductor layer patterning | Khanh B. Nguyen, Harry J. Levinson, Scott A. Bell, Fei Wang, Chih-Yuh Yang | 2003-04-08 |
| 6544693 | Pellicle for use in small wavelength lithography and a method for making such a pellicle | Harry J. Levinson | 2003-04-08 |
| 6541360 | Bi-layer trim etch process to form integrated circuit gate structures | Marina V. Plat, Scott A. Bell, Ramkumar Subramanian, Bhanwar Singh | 2003-04-01 |
| 6534418 | Use of silicon containing imaging layer to define sub-resolution gate structures | Marina V. Plat, Scott A. Bell, Ramkumar Subramanian, Bhanwar Singh | 2003-03-18 |
| 6528372 | Sidewall spacer definition of gates | Todd P. Lukanc | 2003-03-04 |
| 6458691 | Dual inlaid process using an imaging layer to protect via from poisoning | Ramkumar Subramanian, Marina V. Plat, Bhanwar Singh | 2002-10-01 |
| 6448164 | Dark field image reversal for gate or line patterning | Ramkumar Subramanian, Marina V. Plat, Todd P. Lukanc | 2002-09-10 |
| 6440640 | Thin resist with transition metal hard mask for via etch application | Chih-Yuh Yang, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell | 2002-08-27 |
| 6423650 | Ultra-thin resist coating quality by increasing surface roughness of the substrate | Marina V. Plat, Michael K. Templeton, Bhanwar Singh | 2002-07-23 |
| 6423475 | Sidewall formation for sidewall patterning of sub 100 nm structures | Michael K. Templeton, Kathleen R. Early | 2002-07-23 |