Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6405096 | Method and apparatus for run-to-run controlling of overlay registration | Christopher A. Bode, Richard D. Edwards | 2002-06-11 |
| 6387823 | Method and apparatus for controlling deposition process using residual gas analysis | Thomas J. Sonderman | 2002-05-14 |
| 6379980 | Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination | — | 2002-04-30 |
| 6368883 | Method for identifying and controlling impact of ambient conditions on photolithography processes | Christopher A. Bode | 2002-04-09 |
| 6368879 | Process control with control signal derived from metrology of a repetitive critical dimension feature of a test structure on the work piece | — | 2002-04-09 |
| 6365422 | Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same | Joyce S. Oey Hewett | 2002-04-02 |
| 6360133 | Method and apparatus for automatic routing for reentrant process | William J. Campbell, Christopher A. Bone | 2002-03-19 |
| 6355388 | Method for controlling photoresist strip processes | — | 2002-03-12 |
| 6352867 | Method of controlling feature dimensions based upon etch chemistry concentrations | Terri A. Couteau, William J. Campbell | 2002-03-05 |
| 6348289 | System and method for controlling polysilicon feature critical dimension during processing | Terri A. Couteau, W. Jarrett Campbell | 2002-02-19 |
| 6346426 | Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements | Derick J. Wristers, Jon D. Cheek | 2002-02-12 |
| 6316302 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Jon D. Cheek, Derick J. Wristers | 2001-11-13 |
| 6304999 | Method and apparatus for embedded process control framework in tool systems | Elfido Coss, Jr. | 2001-10-16 |
| 6268227 | Method for controlling photoresist removal processes | — | 2001-07-31 |
| 6245581 | Method and apparatus for control of critical dimension using feedback etch control | Douglas J. Bonser, Matthew A. Purdy, John R. Behnke, James H. Hussey, Jr. | 2001-06-12 |
| 6238937 | Determining endpoint in etching processes using principal components analysis of optical emission spectra with thresholding | Joseph William Wiseman, Hongyu Yue | 2001-05-29 |
| 6239467 | Method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength | Mark I. Gardner, H. Jim Fulford | 2001-05-29 |
| 6228663 | Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength | Mark I. Gardner, H. Jim Fulford | 2001-05-08 |
| 6230069 | System and method for controlling the manufacture of discrete parts in semiconductor fabrication using model predictive control | William J. Campbell, James A. Mullins | 2001-05-08 |
| 6136616 | Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength | H. Jim Fulford, Randy Blair | 2000-10-24 |
| 6133132 | Method for controlling transistor spacer width | John R. Behnke, Matthew A. Purdy | 2000-10-17 |
| 6130414 | Systems and methods for controlling semiconductor processing tools using measured current flow to the tool | — | 2000-10-10 |
| 6124610 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | Jon D. Cheek, Derick J. Wristers | 2000-09-26 |
| 6110785 | Formulation of high performance transistors using gate trim etch process | Thomas E. Spikes, Jr., Mark I. Gardner | 2000-08-29 |
| 5926690 | Run-to-run control process for controlling critical dimensions | Douglas John Downey, Subhash Gupta | 1999-07-20 |