Issued Patents 2018
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162198 | Multiband QAM interface for slab waveguide | Chewn-Pu Jou | 2018-12-25 |
| 10164114 | FinFETs and methods of forming FinFETs | Chin-Hsiang Lin, Tai-Chun Huang | 2018-12-25 |
| 10163797 | Forming interlayer dielectric material by spin-on metal oxide deposition | Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen | 2018-12-25 |
| 10126512 | Differential silicon interface for dielectric slab waveguide | Chewn-Pu Jou | 2018-11-13 |
| 10103102 | Structure and formation method of semiconductor device structure | Jian-Hua Chen, Tai-I Yang, Cheng-Chi Chuang, Chia-Tien Wu, Tien-Lu Lin | 2018-10-16 |
| 10090245 | Semiconductor device structure | Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Jung-Hsun Tsai | 2018-10-02 |
| 10082626 | Adhesion promoter apparatus and method | Chun-Hao Tseng, Ying-Hao Kuo, Kai-Fang Cheng, Hai-Ching Chen | 2018-09-25 |
| 10074607 | Semiconductor device structure with graphene layer | Tai-I Yang, Tien-Lu Lin, Wei-Chen Chu | 2018-09-11 |
| 10068770 | Method and structure for semiconductor device having gate spacer protection layer | Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang | 2018-09-04 |
| 10049919 | Semiconductor device including a target integrated circuit pattern | Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu +1 more | 2018-08-14 |
| 10020259 | Copper etching integration scheme | Chih Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee | 2018-07-10 |
| 10014175 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2018-07-03 |
| 10008382 | Semiconductor device having a porous low-k structure | Bo-Jiun Lin, Hai-Ching Chen | 2018-06-26 |
| 10002826 | Semiconductor device structure with conductive pillar and conductive line and method for forming the same | Tai-I Yang, Yu-Chieh Liao, Tien-Lu Lin | 2018-06-19 |
| 9997404 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2018-06-12 |
| 9985134 | FinFETs and methods of forming FinFETs | Chin-Hsiang Lin, Tai-Chun Huang | 2018-05-29 |
| 9966336 | Hybrid interconnect scheme and methods for forming the same | Chen-Hua Yu | 2018-05-08 |
| 9941157 | Porogen bonded gap filling material in semiconductor manufacturing | Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen | 2018-04-10 |
| 9922927 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue | 2018-03-20 |
| 9910217 | Method of fabrication polymer waveguide | Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen | 2018-03-06 |
| 9911732 | Vertical metal insulator metal capacitor having a high-k dielectric material | Chewn-Pu Jou | 2018-03-06 |
| 9911646 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Shau-Lin Shue | 2018-03-06 |
| 9911623 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee +1 more | 2018-03-06 |
| 9905457 | High boiling temperature solvent additives for semiconductor processing | Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen | 2018-02-27 |
| 9881871 | Schemes for forming barrier layers for copper in interconnect structures | Chen-Hua Yu, Hai-Ching Chen | 2018-01-30 |