Issued Patents 2018
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163654 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2018-12-25 |
| 10014175 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2018-07-03 |
| 9997404 | Method of forming an interconnect structure for a semiconductor device | Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee, Yung-Sung Yen +4 more | 2018-06-12 |
| 9947535 | Trench formation using horn shaped spacer | Tsung-Min Huang, Chung-Ju Lee | 2018-04-17 |
| 9922927 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao | 2018-03-20 |
| 9911646 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue | 2018-03-06 |