Issued Patents 2018
Showing 76–100 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083839 | Sidewall image transfer (SIT) methods with localized oxidation enhancement of sacrificial mandrel sidewall by ion beam exposure | — | 2018-09-25 |
| 10084090 | Method and structure of stacked FinFET | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-09-25 |
| 10083907 | Method and structure for forming on-chip anti-fuse with reduced breakdown voltage | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-09-25 |
| 10083962 | Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition | Fee Li Lie, Eric R. Miller, Sean Teehan | 2018-09-25 |
| 10079292 | Fabrication of vertical field effect transistor structure with controlled gate length | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-09-18 |
| 10079302 | Silicon germanium fin immune to epitaxy defect | Juntao Li, Xin Miao | 2018-09-18 |
| 10079303 | Method to form strained nFET and strained pFET nanowires on a same substrate | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-09-18 |
| 10079287 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2018-09-18 |
| 10079280 | Asymmetric FET | Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang | 2018-09-18 |
| 10079232 | FinFET CMOS with silicon fin n-channel FET and silicon germanium fin p-channel FET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-09-18 |
| 10079304 | Silicon germanium fin immune to epitaxy defect | Juntao Li, Xin Miao | 2018-09-18 |
| 10079181 | P-FET with strained silicon-germanium channel | Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi | 2018-09-18 |
| 10079354 | Vertically aligned carbon nanotube trapezoid FIN structure | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2018-09-18 |
| 10079229 | Resistor fins | Zhenxing Bi, Juntao Li, Peng Xu | 2018-09-18 |
| 10074652 | Vertical FET with reduced parasitic capacitance | Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2018-09-11 |
| 10074730 | Forming stacked nanowire semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2018-09-11 |
| 10069015 | Width adjustment of stacked nanowires | Xin Miao, Ruilong Xie, Tenko Yamashita | 2018-09-04 |
| 10069008 | Vertical transistor pass gate device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-09-04 |
| 10068807 | Uniform shallow trench isolation | Junli Wang, Peng Xu, Chen Zhang | 2018-09-04 |
| 10068898 | On-chip MIM capacitor | Peng Xu | 2018-09-04 |
| 10068970 | Nanowire isolation scheme to reduce parasitic capacitance | Bruce B. Doris, Junli Wang | 2018-09-04 |
| 10068980 | Vertical fin with a gate structure having a modified gate geometry | Peng Xu | 2018-09-04 |
| 10068799 | Self-aligned contact | Xin Miao, Wenyu Xu, Chen Zhang | 2018-09-04 |
| 10062643 | Nickel-silicon fuse for FinFET structures | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2018-08-28 |
| 10062785 | Fin field-effect transistor (FinFET) with reduced parasitic capacitance | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-08-28 |