Issued Patents 2018
Showing 51–75 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10109709 | P-FET with strained silicon-germanium channel | Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi | 2018-10-23 |
| 10103243 | Unipolar spacer formation for finFETS | Peng Xu, Jie Yang | 2018-10-16 |
| 10103246 | Fabrication of a vertical fin field effect transistor (vertical finFET) with a self-aligned gate and fin edges | Xin Miao, Wenyu Xu, Chen Zhang | 2018-10-16 |
| 10103247 | Vertical transistor having buried contact, and contacts using work function metals and silicides | Ruilong Xie, Hui Zang, Tenko Yamashita, Chun-Chen Yeh | 2018-10-16 |
| 10103063 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2018-10-16 |
| 10096698 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2018-10-09 |
| 10096484 | Vertical transistor with a body contact for back-biasing | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-10-09 |
| 10096692 | Vertical field effect transistor with reduced parasitic capacitance | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-10-09 |
| 10096524 | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2018-10-09 |
| 10096674 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Xin Miao, Ruilong Xie, Tenko Yamashita | 2018-10-09 |
| 10096695 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Juntao Li, Peng Xu | 2018-10-09 |
| 10090412 | Vertical transistor with back bias and reduced parasitic capacitance | Xin Miao, Peng Xu, Chen Zhang | 2018-10-02 |
| 10090481 | Fringing field assisted dielectrophoresis assembly of carbon nanotubes | Qing Cao, Shu-Jen Han, Zhengwen Li, Fei Liu | 2018-10-02 |
| 10090411 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-10-02 |
| 10090293 | Integrated device with P-I-N diodes and vertical field effect transistors | Juntao Li, Geng Wang, Qintao Zhang | 2018-10-02 |
| 10090303 | Fabrication of vertical field effect transistors with uniform structural profiles | — | 2018-10-02 |
| 10090307 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-10-02 |
| 10084094 | Wrapped source/drain contacts with enhanced area | Zuoguang Liu, Heng Wu, Peng Xu | 2018-09-25 |
| 10084090 | Method and structure of stacked FinFET | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-09-25 |
| 10084067 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Ramachandra Divakaruni, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2018-09-25 |
| 10083839 | Sidewall image transfer (SIT) methods with localized oxidation enhancement of sacrificial mandrel sidewall by ion beam exposure | — | 2018-09-25 |
| 10083972 | Hybrid logic and SRAM contacts | Veeraraghavan S. Basker, Ali Khakifirooz | 2018-09-25 |
| 10084041 | Method and structure for improving FinFET with epitaxy source/drain | Ali Khakifirooz, Alexander Reznicek, Tenko Yamashita | 2018-09-25 |
| 10083871 | Fabrication of a vertical transistor with self-aligned bottom source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2018-09-25 |
| 10084050 | Semiconductor device with low-K gate cap and self-aligned contact | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2018-09-25 |