Issued Patents 2017
Showing 151–175 of 204 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9620416 | Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2017-04-11 |
| 9614037 | Nano-ribbon channel transistor with back-bias control | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-04-04 |
| 9614040 | Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-04-04 |
| 9613899 | Epitaxial semiconductor fuse for FinFET structure | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2017-04-04 |
| 9613803 | Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same | — | 2017-04-04 |
| 9607990 | Method to form strained nFET and strained pFET nanowires on a same substrate | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-03-28 |
| 9608068 | Substrate with strained and relaxed silicon regions | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Hong He | 2017-03-28 |
| 9608063 | Nanowire transistor structures with merged source/drain regions using auxiliary pillars | Pouya Hashemi, Ali Khakifirooz | 2017-03-28 |
| 9607898 | Simultaneously fabricating a high voltage transistor and a finFET | Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty | 2017-03-28 |
| 9601565 | Zig-zag trench structure to prevent aspect ratio trapping defect escape | Judson R. Holt, Shogo Mochizuki, Melissa A. Smith | 2017-03-21 |
| 9601624 | SOI based FINFET with strained source-drain regions | Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Dominic J. Schepis | 2017-03-21 |
| 9601482 | Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication | Keith E. Fogel, Devendra K. Sadana, Charan V. Surisetty | 2017-03-21 |
| 9595595 | Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-03-14 |
| 9595598 | Semiconductor device including epitaxially formed buried channel region | Jie Deng, Pranita Kerber, Qiqing C. Ouyang | 2017-03-14 |
| 9595525 | Semiconductor device including nanowire transistors with hybrid channels | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-03-14 |
| 9589845 | Fin cut enabling single diffusion breaks | Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Vamsi K. Paruchuri | 2017-03-07 |
| 9590106 | Semiconductor device including epitaxially formed buried channel region | Jie Deng, Pranita Kerber, Qiqing C. Ouyang | 2017-03-07 |
| 9590077 | Local SOI fins with multiple heights | Kangguo Cheng, Joel P. de Souza, Ali Khakifirooz, Dominic J. Schepis | 2017-03-07 |
| 9590037 | p-FET with strained silicon-germanium channel | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2017-03-07 |
| 9589848 | FinFET structures having silicon germanium and silicon channels | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2017-03-07 |
| 9589827 | Shallow trench isolation regions made from crystalline oxides | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Charan V. Surisetty | 2017-03-07 |
| 9583492 | Structure and method for advanced bulk fin isolation | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2017-02-28 |
| 9583599 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2017-02-28 |
| 9583572 | FinFET devices having silicon germanium channel fin structures with uniform thickness | Veeraraghavan S. Basker, Keith E. Fogel, Pouya Hashemi | 2017-02-28 |
| 9583507 | Adjacent strained <100> NFET fins and <110> PFET fins | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi | 2017-02-28 |