Issued Patents 2017
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852981 | III-V compatible anti-fuses | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-12-26 |
| 9842770 | Reflow enhancement layer for metallization structures | Praneet Adusumilli, Alexander Reznicek | 2017-12-12 |
| 9831254 | Multiple breakdown point low resistance anti-fuse structure | Praneet Adusumilli, Adra Carr, Alexander Reznicek | 2017-11-28 |
| 9824967 | Semiconductor resistor structures embedded in a middle-of-the-line (MOL) dielectric | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-11-21 |
| 9812522 | Metal-insulator-metal capacitor fabrication with unitary sputtering process | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-11-07 |
| 9793213 | Ion flow barrier structure for interconnect metallization | James J. Demarest, James J. Kelly, Koichi Motoyama, Christopher J. Penny | 2017-10-17 |
| 9786596 | Fuse formed from III-V aspect ratio structure | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-10-10 |
| 9786595 | Antifuse having comb-like top electrode | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-10-10 |
| 9741812 | Dual metal interconnect structure | Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama | 2017-08-22 |
| 9735165 | Vertically stacked FinFET fuse | Praneet Adusumilli, Alexander Reznicek | 2017-08-15 |
| 9722038 | Metal cap protection layer for gate and contact metallization | Praneet Adusumilli, Hemanth Jagannathan, Alexander Reznicek, Chih-Chao Yang | 2017-08-01 |
| 9613899 | Epitaxial semiconductor fuse for FinFET structure | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-04-04 |
| 9564310 | Metal-insulator-metal capacitor fabrication with unitary sputtering process | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2017-02-07 |