Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
AR

Alexander Reznicek

IBM: 192 patents #2 of 10,852Top 1%
Globalfoundries: 12 patents #25 of 1,311Top 2%
RERenesas Electronics: 1 patents #273 of 915Top 30%
Troy, NY: #1 of 70 inventorsTop 2%
New York: #2 of 12,278 inventorsTop 1%
Overall (2017): #7 of 506,227Top 1%
204 Patents 2017

Issued Patents 2017

Showing 101–125 of 204 patents

Patent #TitleCo-InventorsDate
9716145 Strained stacked nanowire field-effect transistors (FETs) Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-07-25
9704860 Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation Karthik Balakrishnan, Keith E. Fogel, Sivananda K. Kanakasabapathy 2017-07-11
9704753 Minimizing shorting between FinFET epitaxial regions Kangguo Cheng, Balasubramanian Pranatharthiharan, Charan V. Surisetty 2017-07-11
9698145 Implementation of long-channel thick-oxide devices in vertical transistor flow Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-07-04
9691854 Semiconductor device including multiple fin heights Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-06-27
9685328 Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same 2017-06-20
9685510 SiGe CMOS with tensely strained NFET and compressively strained PFET Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-06-20
9685434 Inter-level dielectric layer in replacement metal gates and resistor fabrication Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty 2017-06-20
9685409 Top metal contact for vertical transistor structures Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-06-20
9679969 Semiconductor device including epitaxially formed buried channel region Jie Deng, Pranita Kerber, Qiqing C. Ouyang 2017-06-13
9680018 Method of forming high-germanium content silicon germanium alloy fins on insulator Pouya Hashemi, Renee T. Mo, John A. Ott 2017-06-13
9679763 Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate Kangguo Cheng, Pouya Hashemi, Dominic J. Schepis 2017-06-13
9673296 Semiconductor structure having a source and a drain with reverse facets Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Jinghong Li 2017-06-06
9673307 Lateral bipolar junction transistor with abrupt junction and compound buried oxide Kevin K. Chan, Pouya Hashemi, Tak H. Ning 2017-06-06
9673196 Field effect transistors with varying threshold voltages Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz 2017-06-06
9666489 Stacked nanowire semiconductor device Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-05-30
9666669 Superlattice lateral bipolar junction transistor Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari 2017-05-30
9666493 Semiconductor device structure with 110-PFET and 111-NFET curent flow direction Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki 2017-05-30
9666486 Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate Mona A. Ebrish, Hemanth Jagannathan, Shogo Mochizuki 2017-05-30
9659829 Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS Karthik Balakrishnan, Pouya Hashemi, Sanghoon Lee 2017-05-23
9660059 Fin replacement in a field-effect transistor Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Dominic J. Schepis 2017-05-23
9660032 Method and apparatus providing improved thermal conductivity of strain relaxed buffer Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi 2017-05-23
9659963 Contact formation to 3D monolithic stacked FinFETs Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz 2017-05-23
9659938 Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins Hemanth Jagannathan 2017-05-23
9659931 Fin cut on sit level Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita 2017-05-23