Issued Patents 2017
Showing 51–75 of 204 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773907 | Method to controllably etch silicon recess for ultra shallow junctions | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2017-09-26 |
| 9773913 | Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-09-26 |
| 9773812 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung | 2017-09-26 |
| 9773905 | Strained FinFET by epitaxial stressor independent of gate pitch | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Charan V. Surisetty | 2017-09-26 |
| 9773901 | Bottom spacer formation for vertical transistor | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2017-09-26 |
| 9768262 | Embedded carbon-doped germanium as stressor for germanium nFET devices | Jeffrey L. Dittmar, Keith E. Fogel, Sebastian Naczas, Devendra K. Sadana | 2017-09-19 |
| 9768272 | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity | Pouya Hashemi, Hong He, Tenko Yamashita | 2017-09-19 |
| 9768020 | Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same | — | 2017-09-19 |
| 9761499 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki | 2017-09-12 |
| 9761587 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-09-12 |
| 9761726 | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-09-12 |
| 9761667 | Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-09-12 |
| 9761498 | Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs | Bruce B. Doris, Joshua M. Rubin, Tenko Yamashita | 2017-09-12 |
| 9761608 | Lateral bipolar junction transistor with multiple base lengths | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2017-09-12 |
| 9761609 | Structure having group III-V, Ge and SiGe Fins on insulator | Shogo Mochizuki | 2017-09-12 |
| 9761610 | Strain release in PFET regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2017-09-12 |
| 9761661 | Stacked strained and strain-relaxed hexagonal nanowires | Takashi Ando, Pouya Hashemi, John A. Ott | 2017-09-12 |
| 9754933 | Large area diode co-integrated with vertical field-effect-transistors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-09-05 |
| 9754941 | Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate | Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis | 2017-09-05 |
| 9754967 | Structure for integration of an III-V compound semiconductor on SOI | Hemanth Jagannathan | 2017-09-05 |
| 9754875 | Designable channel FinFET fuse | Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki | 2017-09-05 |
| 9755078 | Structure and method for multi-threshold voltage adjusted silicon germanium alloy devices with same silicon germanium content | Pouya Hashemi, Pranita Kerber, Christine Qiqing Ouyang | 2017-09-05 |
| 9754968 | Structure and method to form III-V, Ge and SiGe fins on insulator | Shogo Mochizuki | 2017-09-05 |
| 9748365 | SiGe and Si FinFET structures and methods for making the same | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2017-08-29 |
| 9748382 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2017-08-29 |