Issued Patents 2017
Showing 26–50 of 204 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9799513 | Localized elastic strain relaxed buffer | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2017-10-24 |
| 9799777 | Floating gate memory in a channel last vertical FET flow | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2017-10-24 |
| 9799600 | Nickel-silicon fuse for FinFET structures | Kangguo Cheng, Keith E. Fogel, Pouya Hashemi | 2017-10-24 |
| 9799730 | FINFETs with high quality source/drain structures | Kangguo Cheng, Ali Khakifirooz, Charan V. Surisetty | 2017-10-24 |
| 9799754 | Contact structure and extension formation for III-V nFET | Veeraraghavan S. Basker | 2017-10-24 |
| 9799736 | High acceptor level doping in silicon germanium | Mona A. Ebrish, Oleg Gluschenkov, Shogo Mochizuki | 2017-10-24 |
| 9799569 | Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-10-24 |
| 9793401 | Vertical field effect transistor including extension and stressors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-17 |
| 9793263 | Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari | 2017-10-17 |
| 9793113 | Semiconductor structure having insulator pillars and semiconductor material on substrate | Dominic J. Schepis, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi | 2017-10-17 |
| 9793114 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Bruce B. Doris, Keith E. Fogel | 2017-10-17 |
| 9786739 | Stacked nanosheets by aspect ratio trapping | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-10 |
| 9786758 | Vertical Schottky barrier FET | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-10 |
| 9786497 | Double aspect ratio trapping | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2017-10-10 |
| 9786782 | Source/drain FinFET channel stressor structure | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-10 |
| 9786595 | Antifuse having comb-like top electrode | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2017-10-10 |
| 9786596 | Fuse formed from III-V aspect ratio structure | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2017-10-10 |
| 9786768 | III-V vertical field effect transistors with tunable bandgap source/drain regions | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-10 |
| 9780194 | Vertical transistor structure with reduced parasitic gate capacitance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-03 |
| 9780088 | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-03 |
| 9780100 | Vertical floating gate memory with variable channel doping profile | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2017-10-03 |
| 9779995 | Highly scaled tunnel FET with tight pitch and method to fabricate same | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2017-10-03 |
| 9780173 | High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2017-10-03 |
| 9780094 | Trench to trench fin short mitigation | Veeraraghavan S. Basker | 2017-10-03 |
| 9773812 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung | 2017-09-26 |