Issued Patents 2016
Showing 101–125 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9356027 | Dual work function integration for stacked FinFET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-05-31 |
| 9349809 | Aspect ratio trapping and lattice engineering for III/V semiconductors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-05-24 |
| 9349808 | Double aspect ratio trapping | Kangguo Cheng, Bruce B. Doris, Alexander Reznicek | 2016-05-24 |
| 9349798 | CMOS structures with selective tensile strained NFET fins and relaxed PFET fins | Bruce B. Doris, Hong He, Joshua M. Rubin | 2016-05-24 |
| 9349594 | Non-planar semiconductor device with aspect ratio trapping | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-05-24 |
| 9349658 | Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material | Ajey Poovannummoottil Jacob, Bruce B. Doris, Kangguo Cheng, Kern Rim | 2016-05-24 |
| 9349861 | Silicon-on-insulator substrates having selectively formed strained and relaxed device regions | Kangguo Cheng, Bruce B. Doris, Devendra K. Sadana | 2016-05-24 |
| 9349840 | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device | Xiuyu Cai, Ruilong Xie, Ajey Poovannummoottil Jacob, Witold P. Maszara, Kangguo Cheng | 2016-05-24 |
| 9349835 | Methods for replacing gate sidewall materials with a low-k spacer | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2016-05-24 |
| 9343550 | Silicon-on-nothing FinFETs | Kangguo Cheng, Alexander Reznicek, Dominic J. Schepis | 2016-05-17 |
| 9343529 | Method of formation of germanium nanowires on bulk substrates | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-05-17 |
| 9337259 | Structure and method to improve ETSOI MOSFETS with back gate | Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Balasubramanian Pranatharthiharan | 2016-05-10 |
| 9337196 | III-V FinFET CMOS with III-V and germanium-containing channel closely spaced | Kangguo Cheng, Alexander Reznicek, Ghavam G. Shahidi | 2016-05-10 |
| 9331201 | Multi-height FinFETs with coplanar topography background | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-05-03 |
| 9330908 | Semiconductor structure with aspect ratio trapping capabilities | Thomas N. Adam, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-05-03 |
| 9324790 | Self-aligned dual-height isolation for bulk FinFET | Murat Kerem Akarvardar, Steven Bentley, Kangguo Cheng, Bruce B. Doris, Jody A. Fronheiser +2 more | 2016-04-26 |
| 9324870 | Fin field effect transistor including asymmetric raised active regions | Veeraraghavan S. Basker, Kangguo Cheng | 2016-04-26 |
| 9324867 | Method to controllably etch silicon recess for ultra shallow junctions | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-04-26 |
| 9324843 | High germanium content silicon germanium fins | Karthik Balakrishnan, John Bruley, Pouya Hashemi, John A. Ott, Alexander Reznicek | 2016-04-26 |
| 9324797 | Gate-all-around nanowire MOSFET and method of formation | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-04-26 |
| 9324796 | Gate-all-around nanowire MOSFET and method of formation | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-04-26 |
| 9324795 | Gate-all-around nanowire MOSFET and method of formation | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-04-26 |
| 9324709 | Self-aligned gate contact structure | Veeraraghavan S. Basker, Kangguo Cheng, Viraj Y. Sardesai, Raghavasimhan Sreenivasan | 2016-04-26 |
| 9318489 | Complex circuits utilizing fin structures | Kangguo Cheng, Bruce B. Doris, Kern Rim | 2016-04-19 |
| 9318582 | Method of preventing epitaxy creeping under the spacer | Veeraraghavan S. Basker, Kangguo Cheng, Sreenivasan Raghavasimhan | 2016-04-19 |