Issued Patents 2002
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501555 | Optical technique to detect etch process termination | Kouros Ghandehari, Bhanwar Singh | 2002-12-31 |
| 6483153 | Method to improve LDD corner control with an in-situ film for local interconnect processing | Paul R. Besser, Minh Van Ngo | 2002-11-19 |
| 6479411 | Method for forming high quality multiple thickness oxide using high temperature descum | Jusuke Ogura | 2002-11-12 |
| 6479348 | Method of making memory wordline hard mask extension | Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jean Y. Yang +2 more | 2002-11-12 |
| 6475847 | Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Chi Chang +1 more | 2002-11-05 |
| 6475867 | Method of forming integrated circuit features by oxidation of titanium hard mask | Kouros Ghandehari, Bhanwar Singh | 2002-11-05 |
| 6465835 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2002-10-15 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Narbeh Derhacobian, Janet Wang, Tuan Pham, Ravi Sunkavalli +1 more | 2002-10-15 |
| 6461951 | Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers | Paul R. Besser, Yowjuang W. Liu | 2002-10-08 |
| 6461973 | Method for forming high quality multiple thickness oxide layers by reducing descum induced defects | Jusuke Ogura | 2002-10-08 |
| 6461923 | Sidewall spacer etch process for improved silicide formation | Paul R. Besser, Susan H. Chen | 2002-10-08 |
| 6455373 | Semiconductor device having gate edges protected from charge gain/loss | Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Yu Sun, Chi Chang | 2002-09-24 |
| 6448608 | Capping layer | Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2002-09-10 |
| 6445051 | Method and system for providing contacts with greater tolerance for misalignment in a flash memory | Mark S. Chang, Hao Fang, King Wai Kelwin Ko, John Jianshi Wang, Michael K. Templeton +1 more | 2002-09-03 |
| 6444539 | Method for producing a shallow trench isolation filled with thermal oxide | Yu Sun, Yue-Song He, Tatsuya Kajita, Mark S. Chang, Chi Chang +1 more | 2002-09-03 |
| 6444530 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey +4 more | 2002-09-03 |
| 6431182 | Plasma treatment for polymer removal after via etch | Mohammad R. Rakhshandehroo, Mark S. Chang | 2002-08-13 |
| 6432618 | Method for forming high quality multiple thickness oxide layers by reducing descum induced defects | Jusuke Ogura | 2002-08-13 |
| 6420752 | Semiconductor device with self-aligned contacts using a liner oxide layer | Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Chi Chang +1 more | 2002-07-16 |
| 6400030 | Self-aligning vias for semiconductors | Fei Wang, Robin Cheung, Mark S. Chang, Richard J. Huang | 2002-06-04 |
| 6391729 | Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding | — | 2002-05-21 |
| 6369416 | Semiconductor device with contacts having a sloped profile | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2002-04-09 |
| 6342415 | Method and system for providing reduced-sized contacts in a semiconductor device | Tuan Pham, Mark T. Ramsbey, Yu Sun | 2002-01-29 |