Issued Patents 2002
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6490205 | Method of erasing a non-volatile memory cell using a substrate bias | Ravi Sunkavalli | 2002-12-03 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-22 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Narbeh Derhacobian, Angela T. Hui, Tuan Pham, Ravi Sunkavalli +1 more | 2002-10-15 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-15 |
| 6459618 | Method of programming a non-volatile memory cell using a drain bias | — | 2002-10-01 |
| 6456536 | Method of programming a non-volatile memory cell using a substrate bias | Daniel Sobek, Timothy Thurgate, Narbeh Derhacobian | 2002-09-24 |
| 6456533 | Higher program VT and faster programming rates based on improved erase methods | Darlene Hamilton, Narbeh Derhacobian, Kulachet Tanpairoj | 2002-09-24 |
| 6456531 | Method of drain avalanche programming of a non-volatile memory cell | Sameer Haddad | 2002-09-24 |
| 6410956 | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Vei-Han Chan, Scott Luning, Mark Randolph, Nicholas H. Tripsas, Daniel Sobek +2 more | 2002-06-25 |