Issued Patents 2002
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6493261 | Single bit array edges | Darlene Hamilton, Kulachet Tanpairoj, Narbeh Derhacobian, Michael A. Van Buskirk | 2002-12-10 |
| 6490205 | Method of erasing a non-volatile memory cell using a substrate bias | Janet Wang | 2002-12-03 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-22 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-15 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Narbeh Derhacobian, Janet Wang, Angela T. Hui, Tuan Pham +1 more | 2002-10-15 |
| 6452840 | Feedback method to optimize electric field during channel erase of flash memory devices | Lee Cleveland, Sameer Haddad, Richard Fastow, Tim Thurgate | 2002-09-17 |
| 6442074 | Tailored erase method using higher program VT and higher negative gate erase | Darlene Hamilton, Kulachet Tanpairoj, Narbeh Derhacobian | 2002-08-27 |
| 6385093 | I/O partitioning system and methodology to reduce band-to-band tunneling current during erase | Edward V. Bautista, Jr., Kazuhiro Kurihara, Feng Pan, Weng Fook Lee, Darlene Hamilton | 2002-05-07 |