Issued Patents 2002
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501681 | Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories | Narbeh Derhacobian | 2002-12-31 |
| 6492675 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Chi Chang | 2002-12-10 |
| 6493261 | Single bit array edges | Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli, Narbeh Derhacobian | 2002-12-10 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2002-10-22 |
| 6470414 | Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture | Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny C. Chen | 2002-10-22 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2002-10-15 |