CC

Chi Chang

AM AMD: 12 patents #47 of 1,128Top 5%
Fujitsu Limited: 3 patents #218 of 3,085Top 8%
📍 Redwood City, CA: #2 of 374 inventorsTop 1%
🗺 California: #138 of 26,763 inventorsTop 1%
Overall (2002): #1,143 of 266,432Top 1%
12
Patents 2002

Issued Patents 2002

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
6492675 Flash memory array with dual function control lines and asymmetrical source and drain junctions Michael A. Van Buskirk 2002-12-10
6475847 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Angela T. Hui +1 more 2002-11-05
6469939 Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process Zhigang Wang, Richard Fastow, Sheung-Hee Park, Sameer Haddad 2002-10-22
6455373 Semiconductor device having gate edges protected from charge gain/loss Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Angela T. Hui, Yu Sun 2002-09-24
6444530 Process for fabricating an integrated circuit with a self-aligned contact Hung-Sheng Chen, Unsoon Kim, Yu Sun, Mark T. Ramsbey, Mark Randolph +4 more 2002-09-03
6444539 Method for producing a shallow trench isolation filled with thermal oxide Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark S. Chang +1 more 2002-09-03
6429108 Non-volatile memory device with encapsulated tungsten gate and method of making same Richard J. Huang, Keizaburo Yoshie, Yu Sun 2002-08-06
6420752 Semiconductor device with self-aligned contacts using a liner oxide layer Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Angela T. Hui +1 more 2002-07-16
6399984 Species implantation for minimizing interface defect density in flash memory devices Yider Wu, Mark T. Ramsbey, Yu Sun, Tuan Pham, Jean Y. Yang 2002-06-04
6381179 Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure Narbeh Derhacobian, Michael Van Buskirk, Daniel Sobek 2002-04-30
6356482 Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure Narbeh Derhacobian, Michael Van Buskirk, Daniel Sobek 2002-03-12
6346467 Method of making tungsten gate MOS transistor and memory cell by encapsulating Richard J. Huang, Keizaburo Yoshie, Yu Sun 2002-02-12