ND

Narbeh Derhacobian

AM AMD: 12 patents #47 of 1,128Top 5%
Fujitsu Limited: 2 patents #445 of 3,085Top 15%
📍 Belmont, CA: #1 of 132 inventorsTop 1%
🗺 California: #138 of 26,763 inventorsTop 1%
Overall (2002): #1,041 of 266,432Top 1%
12
Patents 2002

Issued Patents 2002

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
6501681 Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories Michael A. Van Buskirk 2002-12-31
6493261 Single bit array edges Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli, Michael A. Van Buskirk 2002-12-10
6468865 Method of simultaneous formation of bitline isolation and periphery oxide Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more 2002-10-22
6465303 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory Mark T. Ramsbey, Janet Wang, Angela T. Hui, Tuan Pham, Ravi Sunkavalli +1 more 2002-10-15
6465306 Simultaneous formation of charge storage and bitline to wordline isolation Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more 2002-10-15
6456536 Method of programming a non-volatile memory cell using a substrate bias Daniel Sobek, Timothy Thurgate, Janet Wang 2002-09-24
6456533 Higher program VT and faster programming rates based on improved erase methods Darlene Hamilton, Janet Wang, Kulachet Tanpairoj 2002-09-24
6442074 Tailored erase method using higher program VT and higher negative gate erase Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli 2002-08-27
6381179 Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure Michael Van Buskirk, Chi Chang, Daniel Sobek 2002-04-30
6369433 High voltage transistor with low body effect and low leakage Pau-Ling Chen, Hao Fang 2002-04-09
6356482 Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure Michael Van Buskirk, Chi Chang, Daniel Sobek 2002-03-12
6351017 High voltage transistor with modified field implant mask Hao Fang 2002-02-26