Issued Patents 2002
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500755 | Resist trim process to define small openings in dielectric layers | Srikanteswara Dakshina-Murthy, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin +2 more | 2002-12-31 |
| 6492258 | METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY | Minh Van Ngo, Matthew S. Buynoski, John Caffall, Nick Maccrae, Richard J. Huang +1 more | 2002-12-10 |
| 6489240 | Method for forming copper interconnects | John A. Iacoponi, Frederick N. Hause, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more | 2002-12-03 |
| 6483153 | Method to improve LDD corner control with an in-situ film for local interconnect processing | Angela T. Hui, Minh Van Ngo | 2002-11-19 |
| 6475874 | Damascene NiSi metal gate high-k transistor | Qi Xiang, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-11-05 |
| 6465334 | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Matthew S. Buynoski, Paul L. King, Eric N. Paton, Qi Xiang | 2002-10-15 |
| 6465349 | Nitrogen-plasma treatment for reduced nickel silicide bridging | Minh Van Ngo, Christy Mei-Chu Woo, Robert A. Huertas | 2002-10-15 |
| 6465309 | Silicide gate transistors | Qi Xiang, Matthew S. Buynoski, John Foster, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6461951 | Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers | Angela T. Hui, Yowjuang W. Liu | 2002-10-08 |
| 6461923 | Sidewall spacer etch process for improved silicide formation | Angela T. Hui, Susan H. Chen | 2002-10-08 |
| 6458679 | Method of making silicide stop layer in a damascene semiconductor structure | Eric N. Paton, Matthew S. Buynoski, Qi Xiang, Paul L. King, John Foster | 2002-10-01 |
| 6455425 | Selective deposition process for passivating top interface of damascene-type Cu interconnect lines | Darrell M. Erb, Sergey Lopatin | 2002-09-24 |
| 6444567 | Process for alloying damascene-type Cu interconnect lines | Darrell M. Erb | 2002-09-03 |
| 6444513 | Metal gate stack with etch stop layer having implanted metal species | Srikanteswara Dakshina-Murthy | 2002-09-03 |
| 6440868 | Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process | Qi Xiang, Matthew S. Buynoski | 2002-08-27 |
| 6440867 | Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process | Qi Xiang, Matthew S. Buynoski | 2002-08-27 |
| 6436840 | Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process | Matthew S. Buynoski, Qi Xiang | 2002-08-20 |
| 6432805 | Co-deposition of nitrogen and metal for metal silicide formation | Eric N. Paton, Minh Van Ngo | 2002-08-13 |
| 6429128 | Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface | Minh Van Ngo, Larry Zhao | 2002-08-06 |
| 6413846 | Contact each methodology and integration scheme | Errol Todd Ryan, Frederick N. Hause, Frank Mauersberger, William S. Brennan, John A. Iacoponi +1 more | 2002-07-02 |
| 6406993 | Method of defining small openings in dielectric layers | Srikanteswara Dakshina-Murthy, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin +2 more | 2002-06-18 |
| 6392280 | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Qi Xiang, Matthew S. Buynoski | 2002-05-21 |
| 6391750 | Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness | Susan H. Chen | 2002-05-21 |
| 6387767 | Nitrogen-rich silicon nitride sidewall spacer deposition | Minh Van Ngo, Christy Mei-Chu Woo, George Jonathan Kluth | 2002-05-14 |
| 6383947 | Anti-reflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies | Bhanwar Singh, Darrell M. Erb, Susan H. Chen, Carmen Morales | 2002-05-07 |