Issued Patents 2002
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492258 | METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY | Paul R. Besser, Matthew S. Buynoski, John Caffall, Nick Maccrae, Richard J. Huang +1 more | 2002-12-10 |
| 6472336 | Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material | Suzette K. Pangrle, Richard J. Huang | 2002-10-29 |
| 6429141 | Method of manufacturing a semiconductor device with improved line width accuracy | Bhanwar Singh, Dawn Hopper, Carmen Morales | 2002-08-06 |
| 6406996 | Sub-cap and method of manufacture therefor in integrated circuit capping layers | Joffre F. Bernard, Tim Z. Hossain | 2002-06-18 |