FH

Frederick N. Hause

AM AMD: 16 patents #25 of 1,128Top 3%
📍 Palm Bay, FL: #1 of 65 inventorsTop 2%
🗺 Florida: #10 of 3,788 inventorsTop 1%
Overall (2002): #498 of 266,432Top 1%
16
Patents 2002

Issued Patents 2002

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
6491799 Method for forming a thin dielectric layer Karsten Wieczorek, Manfred Horstmann 2002-12-10
6489240 Method for forming copper interconnects John A. Iacoponi, Paul R. Besser, Frank Mauersberger, Errol Todd Ryan, William S. Brennan +1 more 2002-12-03
6458678 Transistor formed using a dual metal process for gate and source/drain region Thomas E. Spikes, Jr., David Wu 2002-10-01
6429052 Method of making high performance transistor with a reduced width gate electrode and device comprising same Mark I. Gardner, John J. Bush 2002-08-06
6426262 Method of analyzing the effects of shadowing of angled halo implants Mark B. Fuselier, Jon D. Cheek, Marilyn I. Wright 2002-07-30
6413846 Contact each methodology and integration scheme Paul R. Besser, Errol Todd Ryan, Frank Mauersberger, William S. Brennan, John A. Iacoponi +1 more 2002-07-02
6410409 Implanted barrier layer for retarding upward diffusion of substrate dopant Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more 2002-06-25
6410967 Transistor having enhanced metal silicide and a self-aligned gate electrode Mark I. Gardner, Charles E. May 2002-06-25
6403445 Enhanced trench isolation structure Mark I. Gardner, Charles E. May 2002-06-11
6380055 Dopant diffusion-retarding barrier region formed within polysilicon gate layer Mark I. Gardner, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more 2002-04-30
6376350 Method of forming low resistance gate electrode Michael Duane, Jeffrey C. Haines 2002-04-23
6372588 Method of making an IGFET using solid phase diffusion to dope the gate, source and drain Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more 2002-04-16
6358826 Device improvement by lowering LDD resistance with new spacer/silicide process Manfred Horstmann, Karsten Wieczorek 2002-03-19
6352885 Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same Karsten Wieczorek, Manfred Horstmann 2002-03-05
6346463 Method for forming a semiconductor device with a tailored well profile Akif Sultan 2002-02-12
6337217 Method and apparatus for improved focus in optical processing Karen Turnquest 2002-01-08