Issued Patents 2002
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495881 | Programmable read only memory in CMOS process flow | Shafqat Ahmed, Hemanshu Bhatt, Robindranath Banerjee | 2002-12-17 |
| 6482075 | Process for planarizing an isolation structure in a substrate | Hemanshu Bhatt, Shafqat Ahmed, Robindranath Banerjee | 2002-11-19 |
| 6452412 | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography | Richard W. Jarvis, Iraj Emami | 2002-09-17 |
| 6451657 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | Mark I. Gardner, H. Jim Fulford | 2002-09-17 |
| 6432812 | Method of coupling capacitance reduction | — | 2002-08-13 |
| 6420220 | Method of forming electrode for high performance semiconductor devices | Mark I. Gardner, H. Jim Fulford | 2002-07-16 |
| 6410967 | Transistor having enhanced metal silicide and a self-aligned gate electrode | Frederick N. Hause, Mark I. Gardner | 2002-06-25 |
| 6403445 | Enhanced trench isolation structure | Mark I. Gardner, Frederick N. Hause | 2002-06-11 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration | Mark I. Gardner, H. Jim Fulford | 2002-03-26 |
| 6348413 | High pressure N2 RTA process for TiS2 formation | Timothy Z. Hossain | 2002-02-19 |
| 6338992 | Programmable read only memory in CMOS process flow | Shafqat Ahmed, Hemanshu Bhatt, Robindranath Banerjee | 2002-01-15 |