Issued Patents 2002
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500681 | Run-to-run etch control by feeding forward measured metal thickness | Craig W. Christian | 2002-12-31 |
| 6483157 | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area | Mark I. Gardner | 2002-11-19 |
| 6454899 | Apparatus for filling trenches | William J. Campbell, Christopher H. Raeder, Craig W. Christian, Thomas J. Sonderman | 2002-09-24 |
| 6451657 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | Mark I. Gardner, Charles E. May | 2002-09-17 |
| 6433400 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | Mark I. Gardner, Derick J. Wristers | 2002-08-13 |
| 6420220 | Method of forming electrode for high performance semiconductor devices | Mark I. Gardner, Charles E. May | 2002-07-16 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2002-06-25 |
| 6388298 | Detached drain MOSFET | Mark I. Gardner | 2002-05-14 |
| 6380554 | Test structure for electrically measuring the degree of misalignment between successive layers of conductors | John J. Bush, Mark I. Gardner | 2002-04-30 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer | Mark I. Gardner, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2002-04-30 |
| 6376330 | Dielectric having an air gap formed between closely spaced interconnect lines | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan | 2002-04-23 |
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain | Derick J. Wristers, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2002-04-16 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration | Mark I. Gardner, Charles E. May | 2002-03-26 |
| 6359461 | Test structure for determining the properties of densely packed transistors | John J. Bush, Jon D. Cheek | 2002-03-19 |
| 6355955 | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation | Mark I. Gardner, Daniel Kadosh | 2002-03-12 |
| 6353253 | Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, Mark W. Michael, William S. Brennan | 2002-03-05 |