Issued Patents 2002
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492210 | Method for fully self-aligned FET technology | Manfred Horstmann, Rolf Stephan, Michael Raab | 2002-12-10 |
| 6491799 | Method for forming a thin dielectric layer | Frederick N. Hause, Manfred Horstmann | 2002-12-10 |
| 6436724 | Method of monitoring the temperature of a rapid thermal anneal process in semiconductor manufacturing and a test wafer for use in this method | Manfred Horstmann, Christian Krüger | 2002-08-20 |
| 6423634 | Method of forming low resistance metal silicide region on a gate electrode of a transistor | Michael Raab, Rolf Stephan | 2002-07-23 |
| 6410410 | Method of forming lightly doped regions in a semiconductor device | Thomas Feudel, Manfred Horstmann | 2002-06-25 |
| 6383906 | Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption | Nicholas J. Kepler, Paul R. Besser, Larry Wang | 2002-05-07 |
| 6380040 | Prevention of dopant out-diffusion during silicidation and junction formation | Nick Kepler, Larry Wang, Paul R. Besser | 2002-04-30 |
| 6358826 | Device improvement by lowering LDD resistance with new spacer/silicide process | Frederick N. Hause, Manfred Horstmann | 2002-03-19 |
| 6352885 | Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same | Frederick N. Hause, Manfred Horstmann | 2002-03-05 |
| 6344397 | Semiconductor device having a gate electrode with enhanced electrical characteristics | Manfred Horstmann, Bernd Engelmann | 2002-02-05 |